Patent US4943837A successfully refreshed from Google Patents.
US4943837A
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US
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Thin film semiconductor device and method of fabricating the same
Assignee: Hitachi Ltd
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Filing: 1988-03-10
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Granted: 1990-07-24
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Expires: 2008-03-10
Abstract
Abstract A thin film transistor and a method of fabricating the transistor are disclosed. The gate electrode of this thin film transistor is made small in thickness so that active hydrogen for hydrogenating passivation can penetrate in a surface layer of channel region having substantially uniform thickness, through the gate electrode. Thus, hydrogenation can be effectively carried out for the thin film transistor, independently of the length of a channel formed in the transistor.
Inventors
- 👤 Nobutake Konishi
- 👤 Kikuo Ono
- 👤 Takaya Suzuki
- 👤 Kenji Miyata
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 05:04
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/67; H10D30/6729; H10D30/673; H10D30/6731; H10D30/6704; H10D30/6713; H10D30/674; H10D30/6741; H10D30/6743; H10D30/6745; H10D30/6746; H10D30/6757; H10P; H10P14/00; H10P14/60; H10P14/65; H10P14/6502; H10P14/6512; H10P14/6514; Y; Y10; Y10S; Y10S438/00; Y10S438/958
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
206 words
A thin film semiconductor device which includes a silicon layer formed on an insulating substrate and made of one of amorphous silicon and polycrystalline silicon, a gate electrode formed over the silicon layer through an insulating film and made of one of amorphous silicon and polycrystalline silicon, source and drain regions formed in the silicon layer so that the projection of the gate electrode onto the silicon layer is interposed between the source and drain regions, a channel region beneath the gate electrode and the insulating film, and source and drain electrodes kept in ohmic contact with the source and drain regions, respectively, wherein the thickness of the gate electrode is made less than or equal to 1,500 Å, whereby an active element for passivation can penetrate through the gate electrode into a surface layer of the entire channel region, which surface layer has a substantially uniform thickness, so that a passivated surface layer of the channel region, having a substantially uniform thickness for the entire channel region, can be achieved, and wherein the device further includes said passivated surface layer, having said active element for passivation therein so as to provide said passivated surface layer, having the substantially uniform thickness, for the entire channel region.
Claim 2
Dependent Claim
206 words
A thin film semiconductor device which includes a silicon layer formed on an insulating substrate and made of one of amorphous silicon and polycrystalline silicon, a gate electrode formed over the silicon layer through an insulating film and made of one of amorphous silicon and polycrystalline silicon, source and drain regions formed in the silicon layer so that the projection of the gate electrode onto the silicon layer is interposed between the source and drain regions, a channel region beneath the gate electrode and the insulating film, and source and drain electrodes kept in ohmic contact with the source and drain regions, respectively, wherein the thickness of the gate electrode is made less than or equal to 1,500 Å, whereby an active element for passivation can penetrate through the gate electrode into a surface layer of the entire channel region, which surface layer has a substantially uniform thickness, so that a passivated surface layer of the channel region, having a substantially uniform thickness for the entire channel region, can be achieved, and wherein the device further includes said passivated surface layer, having said active element for passivation therein so as to provide said passivated surface layer, having the substantially uniform thickness, for the entire channel region.
Claim 3
Dependent Claim
35 words
A thin film semiconductor device according to claim 1, wherein the active element penetrates through the gate electrode into that surface layer, of the channel region, which has a thickness of 300 Å or more.
Claim 4
Dependent Claim
21 words
A thin film semiconductor device according to claim 1, wherein the source and drain regions are formed on the insulating substrate.
Claim 5
Dependent Claim
21 words
A thin film semiconductor device according to claim 1, wherein the source and drain electrodes are formed on the silicon layer.
Claim 6
Dependent Claim
18 words
A thin film semiconductor device according to claim 1, wherein the insulating film is a silicon oxide film.
Claim 7
Dependent Claim
32 words
A thin film semiconductor device according to claim 1, wherein the thickness of the gate electrode is greater than or equal to 100 Å, and less than or equal to 1,500 Å.
Claim 8
Dependent Claim
25 words
A thin film semiconductor device according to claim 1, wherein said channel region is provided in said silicon layer, between said source and drain regions.
Claim 9
Dependent Claim
77 words
A thin film semiconductor device according to claim 1, wherein said silicon layer having the source and drain regions formed therein includes first and second parts, respectively, having the source region and the drain region formed therein, the first and second parts being spaced from each other, and wherein said channel region is formed in a further silicon layer, the further silicon layer being formed on and between the first and second parts of the silicon layer.
Claim 10
Dependent Claim
24 words
A thin film semiconductor device according to claim 1, wherein said active element for passivation is hydrogen, the passivation being a plasma hydrogenating passivation.
Claim 11
Dependent Claim
224 words
A thin film semiconductor device which includes a silicon layer formed on an insulating substrate and made of one of amorphous silicon and polycrystalline silicon, a gate electrode formed over the silicon layer through an insulating film and made of one of amorphous silicon and polycrystalline silicon, source and drain regions formed in the silicon layer so that the projection of the gate electrode onto the silicon layer is interposed between the source and drain regions, a channel region beneath the gate electrode and the insulating film, the length of the channel region beneath the gate electrode being greater than or equal to 10 μm, and source and drain electrodes kept in ohmic contact with the source and drain regions, respectively, wherein the thickness of the gate electrode is made less than or equal to 1,500 Å, whereby an active element for passivation can penetrate through the gate electrode into a surface layer of the entire channel region, which surface layer has a substantially uniform thickness, so that a passivated surface layer of the channel region, having a substantially uniform thickness for the entire channel region, can be achieved, and wherein the device further includes said passivated surface layer, having said active element for passivation therein so as to provide said passivated surface layer, having the substantially uniform thickness, for the entire channel region.
Claim 12
Dependent Claim
224 words
A thin film semiconductor device which includes a silicon layer formed on an insulating substrate and made of one of amorphous silicon and polycrystalline silicon, a gate electrode formed over the silicon layer through an insulating film and made of one of amorphous silicon and polycrystalline silicon, source and drain regions formed in the silicon layer so that the projection of the gate electrode onto the silicon layer is interposed between the source and drain regions, a channel region beneath the gate electrode and the insulating film, the length of the channel region beneath the gate electrode being greater than or equal to 10 μm, and source and drain electrodes kept in ohmic contact with the source and drain regions, respectively, wherein the thickness of the gate electrode is made less than or equal to 1,500 Å, whereby an active element for passivation can penetrate through the gate electrode into a surface layer of the entire channel region, which surface layer has a substantially uniform thickness, so that a passivated surface layer of the channel region, having a substantially uniform thickness for the entire channel region, can be achieved, and wherein the device further includes said passivated surface layer, having said active element for passivation therein so as to provide said passivated surface layer, having the substantially uniform thickness, for the entire channel region.
Claim 13
Dependent Claim
32 words
A thin film semiconductor device according to claim 10, wherein the channel region, having a length beneath the gate electrode greater than or equal to 10 μm, is in the silicon layer.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-07-23 | 1994-01-22 | 1994-07-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-07-23 | 1998-01-22 | 1998-07-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-07-23 | 2002-01-22 | 2002-07-24 | $7700.00 | Window Closed / Lapsed |