Delay circuit for semiconductor integrated circuit devices

Claim 2

A delay circuit for a semiconductor integrated circuit device, comprising: (a) first circuit means for receiving an input signal and for selectively executing charging/discharging in response to said input signal to thereby produce a variable output voltage; (b) second circuit means for receiving a source voltage of said device and for dividing said source voltage to thereby produce a voltage having a predetermined constant potential as a reference voltage; (c) third circuit means, having first and second inputs respectively coupled to said first and second circuit means, for comparing said output voltage of said first circuit means with said reference voltage; (d) fourth circuit means for receiving said input signal and performing a switching operation in response to said input signal to electrically disconnect said second input of said third circuit means from said second circuit means; and (e) fifth circuit means for maintaining said reference voltage at said second input of said third circuit means while said third circuit means is being disconnected from said second circuit means.

Claim 3

The circuit according to claim 1, wherein said second circuit means comprises first and second resistors coupled in series with each other for dividing said source voltage by a predetermined dividing ratio.

Claim 4

The circuit according to claim 2, wherein said fourth circuit means comprises transistor means, provided between said first and second resistors, for changing a voltage division ratio of said first and second resistors thereof in response to said input signal.

Claim 5

The circuit according to claim 3, wherein said transistor means, when rendered nonconductive, electrically disconnects said first and second resistors from said third circuit means.

Claim 6

The circuit according to claim 4, wherein said transistor means comprises a series circuit of two transistors having gate electrodes coupled together.

Claim 7

The circuit according to claim 5, wherein said fourth circuit means further comprises an inverter coupled to said gate electrodes of said two transistors, whereby said input signal is supplied through said inverter to said gate electrodes of said two transistors.

Claim 8

The circuit according to claim 6, wherein said fifth circuit means comprises a capacitor coupled to said second input of said third circuit means.

Claim 9

A delay circuit comprising: (a) charging/discharging circuit means for receiving an input signal and for producing an output voltage in response to said input signal; (b) voltage divider means for receiving a source voltage and dividing said source voltage to provide a reference voltage having a constant potential level, said voltage divider means having first and second resistors coupled in series with each other; (c) comparator means, having an inverting input coupled through a first signal line to said charging/discharging circuit means and a non-inverting input coupled through a second signal line to said voltage divider means, for comparing said output voltage of said charging/discharging circuit means with said reference voltage; (d) switch circuit means, provided between said first and second resistors in said voltage divider means, for receiving said input signal and being rendered selectively nonconductive in response to said input signal to electrically disconnect said first and second resistors from each other and disconnect said second signal line from said first and second resistors, thereby rendering said second signal line electrically floating; and (e) voltage keeping means, coupled to said second signal line, for receiving said reference voltage to be charged when said switch circuit means is rendered conductive, and for maintaining said reference voltage on said second signal line when said switch circuit means is rendered non conductive..

Claim 10

A delay circuit comprising: (a) charging/discharging circuit means for receiving an input signal and for producing an output voltage in response to said input signal; (b) voltage divider means for receiving a source voltage and dividing said source voltage to provide a reference voltage having a constant potential level, said voltage divider means having first and second resistors coupled in series with each other; (c) comparator means, having an inverting input coupled through a first signal line to said charging/discharging circuit means and a non-inverting input coupled through a second signal line to said voltage divider means, for comparing said output voltage of said charging/discharging circuit means with said reference voltage; (d) switch circuit means, provided between said first and second resistors in said voltage divider means, for receiving said input signal and being rendered selectively nonconductive in response to said input signal to electrically disconnect said first and second resistors from each other and disconnect said second signal line from said first and second resistors, thereby rendering said second signal line electrically floating; and (e) voltage keeping means, coupled to said second signal line, for receiving said reference voltage to be charged when said switch circuit means is rendered conductive, and for maintaining said reference voltage on said second signal line when said switch circuit means is rendered non conductive..

Claim 11

The circuit according to claim 8, wherein said switch circuit means comprises: a first transistor provided between said first resistor and said second signal line; and a second transistor provided between said second signal line and said second resistor, said first and second transistors being rendered nonconductive substantially simultaneously.

Claim 12

The circuit according to claim 9, further comprising: (f) control means, coupled to said switch circuit means, for rendering said switch circuit means conductive only during a predetermined time interval prior to occurrence of a change in level of said input signal.

Claim 13

The circuit according to claim 10, wherein said charging/discharging circuit means comprises: a first capacitor, coupled to said first signal line, for selectively receiving said source voltage to execute a charging operation; and a third resistor selectively coupled to said first capacitor, said first capacitor being discharged through said third resistor.

Claim 14

The circuit according to claim 11, wherein said voltage keeping means comprises a second capacitor coupled to said second signal line.

Claim 15

The circuit according to claim 12, wherein said second capacitor has a specific capacitance which is so determined as to make a ratio of a capacitance of said first capacitor to a parasitic capacitance of said first signal line equal to a ratio of a capacitance of said second capacitor to a parasitic capacitance of said second signal line.

Claim 16

The circuit according to claim 13, wherein said first and second transistors have gate electrodes coupled together, and wherein said switch circuit means further comprises an inverter coupled to said gate electrodes of said first and second transistors, said input signal being supplied through said inverter to said gate electrodes of said first and second transistors.

Claim 17

The circuit according to claim 14, wherein said control means comprises an AND gate circuit provided between said inverter and said gates electrodes of said first and second transistors.

Claim 18

The circuit according to claim 15, wherein said comparator means includes a CMOS current mirror type differential amplifier.

Claim 19

A delay circuit for a semiconductor integrated circuit device, comprising: charging/discharging means for receiving an input signal and for producing a variable output signal in response to the input signal; voltage-divider means for receiving a first voltage and for producing a reference voltage having a constant potential level; comparator means having a first input (-) connected to said charging/discharging means and a second input (+) connected to said voltage-divider means, for comparing the output voltage of said charging/discharging means with the reference voltage; said charging/discharging means including a first capacitor connected to a second voltage and said first input; switching means for electrically separating said second input of said comparator means from said voltage-divider means in response to said input signal; and a second capacitor connected to said second voltage and said second input of said comparator means.

Claim 20

A delay circuit for a semiconductor integrated circuit device, comprising: charging/discharging means for receiving an input signal and for producing a variable output signal in response to the input signal; voltage-divider means for receiving a first voltage and for producing a reference voltage having a constant potential level; comparator means having a first input (-) connected to said charging/discharging means and a second input (+) connected to said voltage-divider means, for comparing the output voltage of said charging/discharging means with the reference voltage; said charging/discharging means including a first capacitor connected to a second voltage and said first input; switching means for electrically separating said second input of said comparator means from said voltage-divider means in response to said input signal; and a second capacitor connected to said second voltage and said second input of said comparator means.

Claim 21

The circuit according to claim 17, wherein one of the first and second voltages is a power supply voltage of the semiconductor integrated circuit device.

Claim 22

The circuit according to claim 18, further comprising: first conductor means for supplying the output voltage of said charging/discharging means to said first input (-) of said comparator means; second conductor means for supplying said reference voltage to said second input (+) of said comparator means; said first capacitor being connected to said first conductor means; and said second capacitor means being connected to said second conductor means.

Claim 23

The circuit according to claim 19, wherein said switching means comprises a transistor connected to said second conductor means.

Claim 24

The circuit according to claim 19, wherein said switching means comprises transistors connected to said second conductor means.

Claim 25

The circuit according to claim 19, wherein said switching means comprises a series circuit of transistors having gate electrodes connected to each other.

Claim 26

The circuit according to claim 22, wherein said switching means further comprises an inverter having an input for receiving said input signal and an output connected to said gate electrodes of said transistors.

Claim 27

The device according to claim 19, wherein said first input of said comparator means is an inverting input, and said second input of said comparator is a non-inverting input.

Claim 28

A delay circuit comprising: a charging/discharging circuit connected between a first power supply voltage and a second power supply voltage, said charging/discharging circuit comprising a first capacitor; a reference voltage generation circuit connected between the first and second voltages, for generating a constant voltage; a comparator having an inverting input connected to said charging/discharging circuit and a non-inverting input connected to said reference voltage generation circuit; switching means for selectively disconnecting said comparator from said reference voltage generating circuit; a second capacitor connected to said non-inverting input of said comparator; and said first and second capacitors being connected to one of said first and second voltages.

Claim 29

A delay circuit comprising: a charging/discharging circuit connected between a first power supply voltage and a second power supply voltage, said charging/discharging circuit comprising a first capacitor; a reference voltage generation circuit connected between the first and second voltages, for generating a constant voltage; a comparator having an inverting input connected to said charging/discharging circuit and a non-inverting input connected to said reference voltage generation circuit; switching means for selectively disconnecting said comparator from said reference voltage generating circuit; a second capacitor connected to said non-inverting input of said comparator; and said first and second capacitors being connected to one of said first and second voltages.

Claim 30

The circuit according to claim 25, wherein said reference voltage generation circuit comprises a voltage-divider circuit having resistors.

Claim 31

The circuit according to claim 26, wherein said switching means comprise transistors for electrically separating said resistors from each other and for electrically separating the non-inverting input of said comparator from said resistors of said voltage divider circuit.

Claim 32

The circuit according to claim 27, wherein said charging/discharging circuit further comprises a resistor connected in parallel with said first capacitor.