US4584494A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor timer
Assignee: Fujitsu Ltd
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Filing: 1983-12-29
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Granted: 1986-04-22
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Expires: 2003-12-29
Abstract
Abstract A semiconductor timer has a first MOS capacitor, a charge circuit for charging the first MOS capacitor, and a discharge circuit for discharging the first MOS capacitor. At least one of the charge and discharge circuits includes a transistor connected to the first MOS capacitor in series, and a second MOS capacitor connected to the gate of the transistor. The second MOS capacitor receives clock pulses and intermittently turns on the transistor in response to the clock pulses to gradually charge or discharge the first MOS capacitor.
Inventors
- 👤 Hideki Arakawa
- 👤 Hiromi Kawashima
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 09:00
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/28; H03K17/284; H03K3/00; H03K3/02; H03K3/023; H03K3/0231
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
200 words
A semiconductor timer operatively connectable to receive clock pulses, comprising: a first capacitor; a charge circuit, operatively connected to said first capacitor, for performing a charging operation on said first capacitor; a discharge circuit, operatively connected to said first capacitor, for performing a discharging operation on said first capacitor; monitoring means, operatively connected to said first capacitor and said discharge circuit, for monitoring a voltage across said first capacitor and producing an electrical signal used for starting one of the charging operation of said charge circuit and the discharging operation of said discharge circuit; and clock pulse enabling means, operatively connected to said monitoring means and at least one of said charge and discharge circuits, for enabling and preventing passage of the clock pulses in dependence upon the electrical signal; at least one of said charge circuit and said discharge circuit comprising: a first transistor, operatively connected in series with said first capacitor, having a gate; and a second capacitor, operatively connected to the gate of said first transistor and said clock pulse enabling means, intermittently turning on said first transistor in response to the clock pulses for performing one of the charging and discharging operations on said first capacitor.
Claim 2
Dependent Claim
200 words
A semiconductor timer operatively connectable to receive clock pulses, comprising: a first capacitor; a charge circuit, operatively connected to said first capacitor, for performing a charging operation on said first capacitor; a discharge circuit, operatively connected to said first capacitor, for performing a discharging operation on said first capacitor; monitoring means, operatively connected to said first capacitor and said discharge circuit, for monitoring a voltage across said first capacitor and producing an electrical signal used for starting one of the charging operation of said charge circuit and the discharging operation of said discharge circuit; and clock pulse enabling means, operatively connected to said monitoring means and at least one of said charge and discharge circuits, for enabling and preventing passage of the clock pulses in dependence upon the electrical signal; at least one of said charge circuit and said discharge circuit comprising: a first transistor, operatively connected in series with said first capacitor, having a gate; and a second capacitor, operatively connected to the gate of said first transistor and said clock pulse enabling means, intermittently turning on said first transistor in response to the clock pulses for performing one of the charging and discharging operations on said first capacitor.
Claim 3
Dependent Claim
42 words
A semiconductor timer as claimed in claim 1, wherein said monitoring means produces a first electrical signal used for starting the discharging operation of said discharge circuit and a second electrical signal used for starting the charging operation of said charge circuit.
Claim 4
Dependent Claim
82 words
A semiconductor timer as claimed in claim 2, wherein said semiconductor timer is operatively connectable to receive upper and lower limit voltages and said monitoring means comprises comparing means, operatively connected to said first capacitor, said charge circuit, said discharge circuit and connectable to receive the upper and lower limit voltages, for comparing whether the voltage across said first capacitor is higher than the upper limit voltage and whether the voltage across said first capacitor is lower than the lower limit voltage.
Claim 5
Dependent Claim
120 words
A semiconductor timer as claimed in claim 3, wherein said comparing means comprises: first comparator means, operatively connected to said first capacitor and connectable to receive the upper limit voltage, for comparing the voltage across said first capacitor with the upper limit voltage and producing an output; second comparator means, operatively connected to said first capacitor and connectable to receive the lower limit voltage, for comparing the voltage across said first capacitor with the lower limit voltage and producing an output; and bistable means, operatively connected to said first and second comparator means and said charge and discharge circuits, for producing the first and second electrical signals in response to the outputs from said first and second comparator means, respectively.
Claim 6
Dependent Claim
18 words
A semiconductor timer as claimed in claim 3, wherein the upper and lower limit voltages are constant voltages.
Claim 7
Dependent Claim
36 words
A semiconductor timer as claimed in claim 5, wherein said semiconductor timer is operatively connectable to receive a power supply voltage and the upper and lower limit voltages vary in dependence upon the power supply voltage.
Claim 8
Dependent Claim
99 words
A semiconductor timer as claimed in claim 3, wherein said discharge circuit comprises: said first transistor, operatively connected in series with said first capacitor; and said second capacitor, operatively connected to the gate of said first transistor and connectable to receive the clock pulses, intermittently turning on said first transistor in response to the clock pulses to gradually discharge said first capacitor, and wherein said clock pulse enabling means comprises a second transistor, operatively connected between the gate of said first transistor and ground, having a gate operatively connected to said monitoring means to receive the first electrical signal.
Claim 9
Dependent Claim
63 words
A semiconductor timer as claimed in claim 7, operatively connectable to receive a power supply voltage, wherein said charge circuit comprises a third transistor, operatively connected to said first capacitor and connectable to receive the power supply voltage, having a gate operatively connected to said monitoring means to receive the second electrical signal and applying the power supply voltage to said first capacitor.
Claim 10
Dependent Claim
102 words
A semiconductor timer as claimed in claim 3, wherein said discharge circuit comprises: said first transistor operatively connected in series with said first capacitor; and said second capacitor operatively connected to the gate of said first transistor, and wherein said clock pulse enabling means comprises a second transistor, operatively connected to said second capacitor and to receive the clock pulses, having a gate operatively connected to said monitoring means to receive the first electrical signal and supplying the clock pulses to said second capacitor to turn on said first transistor in response to the clock pulses, thereby gradually discharging said first capacitor.
Claim 11
Dependent Claim
62 words
A semiconductor timer as claimed in claim 9, operatively connectable to receive a power supply voltage, wherein said charge circuit comprises a third transistor, operatively connected to said first capacitor, having a gate operatively connected to said monitoring means to receive the second electrical signal and applying the power supply voltage to said first capacitor in dependence upon the second electrical signal.
Claim 12
Dependent Claim
98 words
A semiconductor timer as claimed in claim 1, wherein said discharge circuit comprises: said first transistor operatively connected in series with said first capacitor; and said second capacitor, operatively connected to the gate of said first transistor and connectable to receive the clock pulses, intermittently turning on said first transistor in response to the clock pulses to gradually discharge said first capacitor, and wherein said clock pulse enabling means comprises a second transistor, operatively connected between the gate of said first transistor and ground, having a gate operatively connected to said monitoring means to receive the electrical signal.
Claim 13
Dependent Claim
66 words
A semiconductor timer as claimed in claim 11, wherein said charge circuit comprises: a third transistor operatively connected in series with said first capacitor and having a gate; and a third capacitor, operatively connected to the gate of said third transistor and connectable to receive the clock pulses, intermittently turning on said third transistor in response to the clock pulses to gradually charge said first capacitor.
Claim 14
Dependent Claim
101 words
A semiconductor timer as claimed in claim 1, wherein said discharge circuit comprises: said first transistor operatively connected in series to said first capacitor; and said second capacitor operatively connected to the gate of said first transistor, and wherein said clock pulse enabling means comprises a second transistor, operatively connected to said second capacitor and to receive the clock pulses, having a gate operatively connected to said monitoring means to receive the electrical signal and supplying the clock pulses to said second capacitor to turn on said first transistor in response to the clock pulses, thereby gradually discharging said first capacitor.
Claim 15
Dependent Claim
66 words
A semiconductor timer as claimed in claim 13, wherein said charge circuit comprises: a third transistor operatively connected in series with said first capacitor, and having a gate; and a third capacitor, operatively connected to the gate of said third transistor and connectable to receive the clock pulses, intermittently turning on said third transistor in response to the clock pulses to gradually charge said first capacitor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-04-21 | 1989-10-21 | 1990-04-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-04-21 | 1993-10-21 | 1994-04-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-04-21 | 1997-10-21 | 1998-04-22 | $7700.00 | Window Closed / Lapsed |