US4943742A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Schottky barrier diode clamp transistor
Assignee: Fujitsu Ltd
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Filing: 1989-04-04
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Granted: 1990-07-24
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Expires: 2009-04-04
Abstract
Abstract A semiconductor device used for, particularly, an output stage of a logic circuit is formed by a Schottky.barrier.diode clamping transistor. A clamping circuit is provided between a collector and a base for clamping a collector potential. The clamping circuit is formed by a Schottky.barrier.diode (SBD) and a series connected resistance coupled to the Schottky.barrier.diode. A collector resistance is divided by resistance division using the series resistance (FIG. 6).
Inventors
- 👤 Toshitaka Fukushima
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 02:20
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/60; H10D84/611; H10D84/613; H03; H03K; H03K19/00; H03K19/01; H03K19/013
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
261 words
A semiconductor device used for a logic circuit including a Schottky.barrier.diode clamping transistor, comprising: a buried layer of a first conductivity type having a first impurity concentration; a collector layer of the first conductivity type on said buried layer, said collector layer having a second impurity concentration which is lower than the first impurity concentration, said collector layer further having a doped contact region of a third impurity concentration higher than the second impurity concentration, said doped contact region being formed between said buried layer and the surface of said collector layer; a base region of a second conductivity type which is opposite to the first conductivity type, said base region being formed at the surface of said collector layer; an emitter region of the first conductivity type formed in the base region; an emitter electrode formed on said emitter region; a base electrode formed on said base region; a collector electrode formed on said doped contact region of said collector layer; and a Schottky contact formed on a portion of said collector layer having the second impurity concentration, said Schottky contact being coupled to said base electrode, a third resistance extending from said Schottky contact through said collector layer, a first resistance extending from said collector contact through said doped contact region to a point in said buried layer, and a second resistance extending from a PN junction between said base region and said collector layer under said emitter region through the collector layer to the point in said buried layer, said first resistance being smaller than said second resistance.
Claim 2
Dependent Claim
261 words
A semiconductor device used for a logic circuit including a Schottky.barrier.diode clamping transistor, comprising: a buried layer of a first conductivity type having a first impurity concentration; a collector layer of the first conductivity type on said buried layer, said collector layer having a second impurity concentration which is lower than the first impurity concentration, said collector layer further having a doped contact region of a third impurity concentration higher than the second impurity concentration, said doped contact region being formed between said buried layer and the surface of said collector layer; a base region of a second conductivity type which is opposite to the first conductivity type, said base region being formed at the surface of said collector layer; an emitter region of the first conductivity type formed in the base region; an emitter electrode formed on said emitter region; a base electrode formed on said base region; a collector electrode formed on said doped contact region of said collector layer; and a Schottky contact formed on a portion of said collector layer having the second impurity concentration, said Schottky contact being coupled to said base electrode, a third resistance extending from said Schottky contact through said collector layer, a first resistance extending from said collector contact through said doped contact region to a point in said buried layer, and a second resistance extending from a PN junction between said base region and said collector layer under said emitter region through the collector layer to the point in said buried layer, said first resistance being smaller than said second resistance.
Claim 3
Dependent Claim
41 words
A semiconductor device as claimed in claim 1, wherein: said collector electrode formed on said doped contact region is positioned between said base region and said Schottky contact; and said point in said buried layer is under said doped contact region.
Claim 4
Dependent Claim
182 words
A semiconductor device used for a logic circuit including a Schottky.barrier.diode clamping transistor, comprising: a substrate; a semiconductor collector layer of a first conductivity type formed on said substrate; a base region of a second conductivity type opposite to the first conductivity type, said base region formed in and at the surface of said collector layer; an emitter region of the first conductivity type formed in said base region; an emitter electrode formed on said emitter region; a base electrode formed on said base region; a collector electrode formed on the surface of said collector layer and positioned adjacent to said emitter electrode; and a Schottky contact formed on a portion of the surface of said collector layer and coupled to said base electrode, said collector layer including a first resistance and a second resistance serially formed from said collector electrode to a PN junction between said base region and said collector layer, and a third resistance formed from said Schottky contact to a point between said first resistance and said second resistance, said first resistance being smaller than said second resistance.
Claim 5
Dependent Claim
182 words
A semiconductor device used for a logic circuit including a Schottky.barrier.diode clamping transistor, comprising: a substrate; a semiconductor collector layer of a first conductivity type formed on said substrate; a base region of a second conductivity type opposite to the first conductivity type, said base region formed in and at the surface of said collector layer; an emitter region of the first conductivity type formed in said base region; an emitter electrode formed on said emitter region; a base electrode formed on said base region; a collector electrode formed on the surface of said collector layer and positioned adjacent to said emitter electrode; and a Schottky contact formed on a portion of the surface of said collector layer and coupled to said base electrode, said collector layer including a first resistance and a second resistance serially formed from said collector electrode to a PN junction between said base region and said collector layer, and a third resistance formed from said Schottky contact to a point between said first resistance and said second resistance, said first resistance being smaller than said second resistance.
Claim 6
Dependent Claim
112 words
A semiconductor device as claimed in claim 3, further comprising: a buried layer of the first conductivity type having a higher impurity concentration than the second impurity concentration of said collector layer, said buried layer being formed between said substrate and said collector layer and positioned under said emitter region, said collector electrode and said Schottky contact; and a collector contact region of the first conductivity type having a higher impurity concentration than the second impurity concentration of said collector layer, said collector contact region being formed in said collector layer between said collector electrode and said buried layer, said collector electrode being formed between said emitter electrode and said Schottky contact.
Claim 7
Dependent Claim
39 words
A semiconductor device as claimed in claim 4, further comprising: an additional collector contact region, an additional collector electrode, and an additional Schottky contact, said additional collector electrode being positioned between said emitter electrode and said additional Schottky contact.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-07-23 | 1994-01-22 | 1994-07-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-07-23 | 1998-01-22 | 1998-07-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-07-23 | 2002-01-22 | 2002-07-24 | $7700.00 | Window Closed / Lapsed |