US4682057A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Circuit design technique to prevent current hogging when minimizing interconnect stripes by paralleling STL or ISL gate inputs
Assignee: Intersil Corp
•
Filing: 1981-09-14
•
Granted: 1987-07-21
•
Expires: 2001-09-14
Abstract
Abstract An STL or ISL logic circuit comprising a plurality of single-input, multiple-output logic gates is provided. Each of these gates has a current source and a transistor including a base, emitter and multiple Schottky diode-to-collector contacts. The bases of the logic gate transistors are tied together to minimize metal interconnect stripes when a fanout greater than that of one gate is needed. Current hogging is reduced by an ohmic collector contact with connects the collector of each transistor together.
Inventors
- 👤 Brent R. Doyle
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 06:37
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/082; H03K19/091; H03K19/0912; H03K19/0915
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
118 words
A logic circuit, comprising: a plurality of single-input, multiple-output logic gates each having a transistor including a base, emitter and collector, said single-input being applied to said base of said transistor, said multiple-outputs being taken from said collector of said transistor through Schottky diodes, said collector having an ohmic collector contact, said bases of said plurality of transistors being connected together and driven by a current source means, said emitters of said plurality of transistors being connected to a common potential node; and contact means interconnecting said ohmic collector contacts of said plurality of gates for reducing current hogging between the bsaes of said transistors when said logic gates have unequal load currents drawn by said multiple outputs.
Claim 2
Dependent Claim
118 words
A logic circuit, comprising: a plurality of single-input, multiple-output logic gates each having a transistor including a base, emitter and collector, said single-input being applied to said base of said transistor, said multiple-outputs being taken from said collector of said transistor through Schottky diodes, said collector having an ohmic collector contact, said bases of said plurality of transistors being connected together and driven by a current source means, said emitters of said plurality of transistors being connected to a common potential node; and contact means interconnecting said ohmic collector contacts of said plurality of gates for reducing current hogging between the bsaes of said transistors when said logic gates have unequal load currents drawn by said multiple outputs.
Claim 3
Dependent Claim
19 words
A logic circuit as defined in claim 1, wherein said single-input, multiple-output logic gates are Schottky transistor logic gates.
Claim 4
Dependent Claim
19 words
A logic circuit as defined in claim 1, wherein said single-input, multiple-output logic gates are integrated Schottky logic gates.
Claim 5
Dependent Claim
24 words
A logic circuit as defined in claim 1 wherein said current source means is a constant current source applied to each of said gates.
Claim 6
Dependent Claim
23 words
A logic circuit as defined in claim 4, wherein said constant current source is a resistor connected to a source of supply voltage.
Claim 7
Dependent Claim
106 words
A logic circuit, comprising: a plurality of single-input, multiple-output logic gates each having a transistor including a base, emitter and collector, said single-input being applied to said base of said transistor, said multiple-outputs being taken from said collector of said transistor through Schottky diodes, said collector having an ohmic collector contact, said bases of said plurality of transistor being connected together and driven by a current source means, said emitters of said plurality of transistors being connected to a common potential node; and contact means interconnecting said ohmic collector contacts for balancing the collector currents of said transistors irrespective of the current loading on said gates.
Claim 8
Dependent Claim
106 words
A logic circuit, comprising: a plurality of single-input, multiple-output logic gates each having a transistor including a base, emitter and collector, said single-input being applied to said base of said transistor, said multiple-outputs being taken from said collector of said transistor through Schottky diodes, said collector having an ohmic collector contact, said bases of said plurality of transistor being connected together and driven by a current source means, said emitters of said plurality of transistors being connected to a common potential node; and contact means interconnecting said ohmic collector contacts for balancing the collector currents of said transistors irrespective of the current loading on said gates.
Claim 9
Dependent Claim
19 words
A logic circuit as defined in claim 6, wherein said single-input, multiple-output logic gates are Schottky transistor logic gates.
Claim 10
Dependent Claim
19 words
A logic circuit as defined in claim 6, wherein said single-input, multiple-output logic gates are integrated Schottky logic gates.
Claim 11
Dependent Claim
24 words
A logic circuit as defined in claim 6, wherein said current source means is a constant current source applied to each of said gates.
Claim 12
Dependent Claim
23 words
A logic circuit as defined in claim 9, wherein said constant current source is a resistor connected to a source of supply voltage.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-07-20 | 1991-01-19 | 1991-07-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-07-20 | 1995-01-19 | 1995-07-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-07-20 | 1999-01-19 | 1999-07-21 | $7700.00 | Window Closed / Lapsed |