Patchification system

Claim 2

A page printer processing system for receiving encoded layout data and painting a bit-mapped image stored in read/write physical memory in which each pixel can be independently painted and for shipping out the bit-mapped image to the printer to print a page, including decoding means for receiving the page layout data and converting it to bit-mapped image data, said physical memory storing data, including the bit-mapped page memory data, at random access physical addresses, means for assigning bit-mapped image data to logical addresses in logical memory, said logical memory divided into logical memory patches, means for mapping the addresses of logical memory patches to the addresses of physical memory patches so constructed and arranged that at least some logical patches containing identical bit-mapped data are mapped to at least one common patch in physical memory, said mapping means comprising a permuter means for transforming non-contiguous logical addresses to contiguous logical addresses within logical patches, and said mapping means making patches in physical memory other than said at least one common patch available for reuse as soon as the portion of the bit-mapped image stored therein has been shipped out and no further reference to that data is required by placing the addresses thereof upon a stack, and means for shipping out the bit-mapped image comprising means for supplying sequential logical addresses of logical patches to said mapping means and wherein said mapping means converts the logical addresses to real addresses of patches in physical memory.

Claim 3

The processing system according to claim 1 in which the mapping means further comprises means for translating the logical addresses associated with logical patches to contiguous physical addresses in said physical memory.

Claim 4

The processing system according to claim 1 in which the assigning means assigns the bit-mapped data to logical patches corresponding to small rectangular regions on the page to be printed.

Claim 5

The processing system according to claim 3 in which the assigning means assign the bit-mapped data to logical patches corresponding to a rectangular area on the page small enough to fit within the borders of the printed page.

Claim 6

The processing system according to claim 1 in which the assigning means assigns logical addresses between the starting addresses of each logical patch which are a power of two.

Claim 7

The processing system according to claim 1 in which the means for assigning, mapping and shipping out provide for the storing and retrieving of other system data in logical memory address space.

Claim 8

A page printer processing system for receiving encoded page layout data and painting a bit-mapped image stored in random access read/write physical memory in which each pixel can be independently printed and for shipping out the bit-mapped image to the printer to print a page, including decoding means for receiving the page layout data and converting it to bit-mapped image data, said physical memory storing data, including the bit-mapped page memory data, at random access physical addresses, means for assigning bit-mapped image data to logical addresses in logical memory, said logical memory divided into logical memory patches, means for mapping the addresses of logical memory patches to the addresses of physical memory patches so constructed and arranged that at least some logical patches containing identical bit-mapped data are mapped to at least one common patch in read/write physical memory associated with the mapping means and the remaining logical patches are mapped to the random access physical memory, said mapping means making patches in random access physical memory available for reuse as soon as the portion of the bit-mapped image stored therein has been shipped out, said mapping means further comprises a permuter means for transforming non-contiguous logical addresses to contiguous logical addresses within logical patches, and means for shipping out the bit-mapped image comprising means for sequentially supplying logical addresses of logical patches to said mapping means and wherein said mapping means converts the logical addresses to real addresses of patches in physical memory such that random access memory cycling is not required when data corresponding to the logical patches containing the identical bit-mapped data are being shipped out directly from the physical memory associated with the mapping means.

Claim 9

A page printer processing system for receiving encoded page layout data and painting a bit-mapped image stored in random access read/write physical memory in which each pixel can be independently printed and for shipping out the bit-mapped image to the printer to print a page, including decoding means for receiving the page layout data and converting it to bit-mapped image data, said physical memory storing data, including the bit-mapped page memory data, at random access physical addresses, means for assigning bit-mapped image data to logical addresses in logical memory, said logical memory divided into logical memory patches, means for mapping the addresses of logical memory patches to the addresses of physical memory patches so constructed and arranged that at least some logical patches containing identical bit-mapped data are mapped to at least one common patch in read/write physical memory associated with the mapping means and the remaining logical patches are mapped to the random access physical memory, said mapping means making patches in random access physical memory available for reuse as soon as the portion of the bit-mapped image stored therein has been shipped out, said mapping means further comprises a permuter means for transforming non-contiguous logical addresses to contiguous logical addresses within logical patches, and means for shipping out the bit-mapped image comprising means for sequentially supplying logical addresses of logical patches to said mapping means and wherein said mapping means converts the logical addresses to real addresses of patches in physical memory such that random access memory cycling is not required when data corresponding to the logical patches containing the identical bit-mapped data are being shipped out directly from the physical memory associated with the mapping means.

Claim 10

The processing system according to claim 7 in which the mapping further comprises means for translating the logical means associated with logical patches to contiguous physical addresses in said physical memory.

Claim 11

The processing system according to claim 7 in which the assigning means assigns the bit-mapped data to logical patches corresponding to small rectangular regions on the page to be printed.

Claim 12

The processing system according to claim 7 in which the assigning means assign the bit-mapped data to logical patches corresponding to a rectangular area on the page small enough to fit within the borders.

Claim 13

The processing system according to claim 7 in which the assigning means assigns logical addresses between the starting addresses of each logical patch which are a power of two.

Claim 14

The processing system according to claim 7 in which the means for assigning, mapping and shipping out provide for the storing and retrieving of other system data in logical memory address space.