Image data buffering circuitry

Claim 2

A memory access control apparatus comprising: a memory (CM 92) having a memory capacity of a plurality of transfer units of data; a writing means (IMC 99, CATWT) for writing data into said memory in a logical address sequence different from a reading logical address sequence effected for reading said data from said memory; a reading means (PRC 35, EORa 94, EORb 95) for reading data from said memory in a logical address sequence different from said memory in a logical address sequence different from a logical address writing sequence effected for writing said data into said memory; an address detecting means (CAQ 93) for detecting a real address at which the read data has been stored in said memory; a correspondence storing means (CAT 91) for storing a correspondence between a real address at which a transfer unit (64 bits x 64 bits) of data is being stored in said memory and the corresponding logical address used to write said transfer unit of data; and a control means (IMC 99, CMWT) for controlling said writing means so as to write, at a read real address detected by said address detecting means, next transfer unit of data, after said transfer unit of data previously stored at said read real address has been read, by specifying said corresponding logical address stored in said correspondence storing means.

Claim 3

A memory access control apparatus as set forth in claim 1, wherein said memory (CM 92) has a real address space to cover within one page of a printing paper, and said correspondence storing means (CAT 91) has a logical space to cover at least two pages of said printing papers.

Claim 4

A memory access control apparatus as set forth in claim 1, wherein said correspondence storing means (CAT 91) comprises, at each logical address, a correspondence establishing bit (NOCELL) indicating whether or not said correspondence is established, said correspondence establishing bit being turned on after said transfer unit of data is written into said memory, and said correspondence establishing bit being turned off after said transfer unit of data is read, a new real address being made to correspond to said logical address at which said correspondence establishing bit is turned off.

Claim 5

A memory access control apparatus as set forth in claim 3, wherein said address detecting means (CAQ 93) is a first-in first-out circuit for storing said read real address after said transfer unit of data is read from said real address and for outputting said read real address, said output read real address being made to correspond to a specified logical address at which said correspondence establishing bit is turned off.

Claim 6

-A memory access control apparatus as set forth in claim 1, wherein said correspondence storing means (CAT 91) comprises, at each logical address, a correspondence inhibiting bit (AOV) indicating whether or not said logical address is permitted to correspond to a real address.

Claim 7

A memory access control apparatus as set forth in claim 5, wherein said control means comprises a blank signal generating means (BLNK) for generating a white area data so as to print out a white space when said correspondence inhibiting bit is in an ON state during a reading operation, or when said correspondence establishing bit is in an OFF state during a reading operation.

Claim 8

A memory access control apparatus as set forth in claim 1, wherein said writing means and said reading means further comprise an address conversion means (EORa 94, EORb 97) for converting the write address or the read address into a lateral accessing address or a vertical accessing address.

Claim 9

Memory access control apparatus, for storing data defining an image made up of a plurality of spacial units (LC), comprising: a memory (CM 92) having a plurality of individually addressable data storage locations (RC); address storage means (CAQ 93) for storing addresses (REAL ADD) of such locations (RC) that are available for the storage of new data; an address correspondence store (CAT 91) having storage areas corresponding respectively to the said spacial units and accessible by means of respective address codes (LOG ADD); writing means for writing the image-defining data, if any, of each spacial unit (LC) in turn, into an individual one of such locations (HC), which location has been selected by taking the address of that location from the address storage means (CAQ 93), and for placing the address of that location in the individual storage area of the correspondence store (CAT 91) that corresponds to the spacial unit (LC) concerned; and reading means for employing the address code (LOG ADD) appropriate to the storage area that corresponds to a selected one of the said spacial units (LC) to read out from the said memory (CM 92) the image-defining data, if any, of the selected spacial unit and to add back to the address storage means the address of the storage location from which that image-defining data has been read out.

Claim 10

Memory access control apparatus, for storing data defining an image made up of a plurality of spacial units (LC), comprising: a memory (CM 92) having a plurality of individually addressable data storage locations (RC); address storage means (CAQ 93) for storing addresses (REAL ADD) of such locations (RC) that are available for the storage of new data; an address correspondence store (CAT 91) having storage areas corresponding respectively to the said spacial units and accessible by means of respective address codes (LOG ADD); writing means for writing the image-defining data, if any, of each spacial unit (LC) in turn, into an individual one of such locations (HC), which location has been selected by taking the address of that location from the address storage means (CAQ 93), and for placing the address of that location in the individual storage area of the correspondence store (CAT 91) that corresponds to the spacial unit (LC) concerned; and reading means for employing the address code (LOG ADD) appropriate to the storage area that corresponds to a selected one of the said spacial units (LC) to read out from the said memory (CM 92) the image-defining data, if any, of the selected spacial unit and to add back to the address storage means the address of the storage location from which that image-defining data has been read out.

Claim 11

Apparatus as claimed in claim 8, having two such address correspondence stores (CAT 91, CAT 92) for use respectively in reading/writing image-defining data of two different images, the operation of the writing and reading means being such that data defining one of the images can be written into the said memory (CM 92) while data defining the other image is being read out from the memory.

Claim 12

Apparatus as claimed in claim 8 or 9, in which each said storage area is provided with means (NOCELL) for indicating whether or not there is image-defining data stored in the memory at a location whose address is stored in the storage area concerned.