US4940967A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Balanced digital infrared detector circuit
Assignee: Philips Communication Security and Imaging Inc
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Filing: 1989-08-31
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Granted: 1990-07-10
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Expires: 2009-08-31
Abstract
Abstract A digital control circuit uses a single infrared detector to control the clock pulse on a digital counter so that the sensitivity control is based on the length of time a change in infrared radiation persists. A pyroelective detector is located in a voltage divider and the intermediate voltage of the divider is digitally compared to the intermediate voltage in a fixed divider as a digitaly controlled pulse is applied to both dividers. Either an increase or a decrease of infrared radiation causes the digital circuit to permit the counter to be activated.
Inventors
- 👤 Edgar M. Smith
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 14:48
CPC Classifications
G; G08; G08B; G08B13/00; G08B13/18; G08B13/189; G08B13/19; Y; Y10; Y10S; Y10S250/00; Y10S250/01
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
524 words
A digital control circuit which initiates an output signal which is synchronized with a clock pulse when infrared radiation to which a sensor is exposed varies from a prescribed level, comprising: an infrared sensor with first and second terminals, the effective resistance of which changes with radiation to which it is exposed, the second terminal being interconnected with a circuit return; a first resistor one terminal of which is connected to the first terminal of the infrared sensor; a capacitor one terminal of which is connected to a second terminal of the first resistor with the second terminal of the capacitor connected to a DC power supply; a second resistor, one terminal of which is connected to the junction of the capacitor and the first resistor: a third resistor one terminal of which is connected to the second terminal of the second resistor, the second terminal of the third resistor being interconnected with a circuit return, the ratio of the resistance values of the second resistor to the third resistor, being the same ratio as the resistance value of the first resistor to the effective resistance value of the infrared sensor when the infrared sensor is exposed to said prescribed level of infrared radiation; a first voltage-sensitive switch and inverter, the input of which is connected to the junction of the infrared sensor and the first resistor; a first digital logic circuit, the reset terminal of which is connected to the output of the first voltage sensitive switch and inverter and with its data terminal connected to the DC power supply; a first diode with its positive terminal connected to the Q bar output of the first digital logic circuit and its negative terminal connected to the junction of the capacitor and the first resistor; a second voltage sensitive switch and inverter, the input of which is connected to the junction of the second resistor and the third resistor; a second digital logic circuit, the reset terminal of which is connected to the output of the second voltage sensitive switch and inverter and with its data terminal connected to the DC power supply; a second diode with its positive terminal connected to the Q bar output of the second digital logic circuit and its negative terminal connected to the junction of the capacitor and the first resistor; a clock generator, the output of which is connected to the clock input terminals of the first and second digital logic circuits; an exclusive OR gate the first input of which is connected to the Q bar output of the first digital logic circuit and the second input of which is connected to the Q bar output of the second digital logic circuit; a time delay the input of which is connected to the clock generator output; and a third digital logic circuit, the data input of which is connected to the output of the exclusive OR gate, the clock input of which is connected to the output of the time delay, and the output of which thereby changes its status when the radiation level to which the infrared sensor is exposed varies from the prescribed level.
Claim 2
Dependent Claim
524 words
A digital control circuit which initiates an output signal which is synchronized with a clock pulse when infrared radiation to which a sensor is exposed varies from a prescribed level, comprising: an infrared sensor with first and second terminals, the effective resistance of which changes with radiation to which it is exposed, the second terminal being interconnected with a circuit return; a first resistor one terminal of which is connected to the first terminal of the infrared sensor; a capacitor one terminal of which is connected to a second terminal of the first resistor with the second terminal of the capacitor connected to a DC power supply; a second resistor, one terminal of which is connected to the junction of the capacitor and the first resistor: a third resistor one terminal of which is connected to the second terminal of the second resistor, the second terminal of the third resistor being interconnected with a circuit return, the ratio of the resistance values of the second resistor to the third resistor, being the same ratio as the resistance value of the first resistor to the effective resistance value of the infrared sensor when the infrared sensor is exposed to said prescribed level of infrared radiation; a first voltage-sensitive switch and inverter, the input of which is connected to the junction of the infrared sensor and the first resistor; a first digital logic circuit, the reset terminal of which is connected to the output of the first voltage sensitive switch and inverter and with its data terminal connected to the DC power supply; a first diode with its positive terminal connected to the Q bar output of the first digital logic circuit and its negative terminal connected to the junction of the capacitor and the first resistor; a second voltage sensitive switch and inverter, the input of which is connected to the junction of the second resistor and the third resistor; a second digital logic circuit, the reset terminal of which is connected to the output of the second voltage sensitive switch and inverter and with its data terminal connected to the DC power supply; a second diode with its positive terminal connected to the Q bar output of the second digital logic circuit and its negative terminal connected to the junction of the capacitor and the first resistor; a clock generator, the output of which is connected to the clock input terminals of the first and second digital logic circuits; an exclusive OR gate the first input of which is connected to the Q bar output of the first digital logic circuit and the second input of which is connected to the Q bar output of the second digital logic circuit; a time delay the input of which is connected to the clock generator output; and a third digital logic circuit, the data input of which is connected to the output of the exclusive OR gate, the clock input of which is connected to the output of the time delay, and the output of which thereby changes its status when the radiation level to which the infrared sensor is exposed varies from the prescribed level.
Claim 3
Dependent Claim
61 words
The digital control circuit of claim 1 further including a digital counter, the clock input of which is connected to the clock generator, and the reset and clock inhibit terminals of which are connected to the Q bar output of the third digital logic circuit, the digital counter being adjustable so that its output signal will occur on any preselected count.
References Cited (Backward Citations)
US3636542A
Cited
US3725888A
Cited
US3840868A
Cited
US3858192A
Cited
US4052716A
Cited
US4242670A
Cited
US4364030A
Cited
US4377808A
Cited
US4570157A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-07-09 | 1994-01-08 | 1994-07-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-07-09 | 1998-01-08 | 1998-07-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-07-09 | 2002-01-08 | 2002-07-10 | $7700.00 | Window Closed / Lapsed |