Abstract Passive intrusion detector logic circuitry is provided which requires two input signals within a specified time period, provides surveillance of all input and output wire terminations, and no possibility of an alarm condition existing at the time when the power is turned on. The circuitry adheres to the Underwriters'' Laboratories internal interference specification and incorporates a walk-test circuit for on-line system tests. The above reduction in the possibility of false alarm rate and the tamper-proof provisions are accomplished using two highnoise-immunity logic hex gates and four transistors. An alarm condition exists when two signals occur at the input to the logic circuitry within five seconds of each other, with all other possibilities seen by the circuitry as a safe condition. This reduces the possibility of false alarms due to sudden surges on the supply line, hot air currents, etc. Also, an alarm condition will occur if any one or all of the external connections to the intrusion detector are cut. An alarm inhibit circuit is incorporated in the logic circuitry to delay any alarm from occuring for approximately 25 seconds to take care of the settling time needed at the preamp section after power turn-on or intermittent power interruptions during the operation.
Intrusion detector logic circuitry for producing an output alarm signal on a predetermined input signal sequence from a detector array comprising, in combination, a. a passive detector array having a predetermined field of view for producing a signal sequence when an intruder moves in the field of view of said detector array, b. means for applying said signal sequence to one of the inputs of a pair of dual input retriggerable one-shot circuits having a single output at which an alarm signal is generated when said signal sequence occurs within a predetermined time interval, c. gating means having first and second inputs and an output, said single output of said pair of retriggerable one-shot circuits coupled to said first input of said gating means for passing an alarm signal to said output thereof, and d. feedback means coupled between the output of said gating means to the other inputs of said dual Input retriggerable oneshot circuits for retriggering said one-shot circuits to assure an alarm signal at the output of said gating means of predetermined duration regardless of the time difference in the input signal sequence as long as the sequence occurs within a predetermined time interval.
Claim 2
Dependent Claim
197 words
Intrusion detector logic circuitry for producing an output alarm signal on a predetermined input signal sequence from a detector array comprising, in combination, a. a passive detector array having a predetermined field of view for producing a signal sequence when an intruder moves in the field of view of said detector array, b. means for applying said signal sequence to one of the inputs of a pair of dual input retriggerable one-shot circuits having a single output at which an alarm signal is generated when said signal sequence occurs within a predetermined time interval, c. gating means having first and second inputs and an output, said single output of said pair of retriggerable one-shot circuits coupled to said first input of said gating means for passing an alarm signal to said output thereof, and d. feedback means coupled between the output of said gating means to the other inputs of said dual Input retriggerable oneshot circuits for retriggering said one-shot circuits to assure an alarm signal at the output of said gating means of predetermined duration regardless of the time difference in the input signal sequence as long as the sequence occurs within a predetermined time interval.
Claim 3
Dependent Claim
52 words
The intrusion logic circuitry set forth in claim 1 having an alarm inhibit circuit coupled between a source of power for the logic circuitry and said second input of said gating means for inhibiting said gating means for a predetermined time interval when the power is first turned on or subsequently interrupted.