Patent US4940905A successfully refreshed from Google Patents.
US4940905A
Expired / Lapsed
US
⏱️ 0.0 years remaining
ECL flip-flop with improved x-ray resistant properties
Assignee: Hitachi Ltd
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Filing: 1989-10-24
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Granted: 1990-07-10
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Expires: 2009-10-24
Abstract
Abstract An ECL flip-flop circuit has a data holding differential transistor pair and a feedback circuit provided between the collectors and bases of this differential transistor pair. The feedback circuit includes a resistor connected between the bases of the data holding differential transistor pair, a pair of switching means for selectively terminating one end or the other of the resistor, and a pair of feedback transistors each adapted to receive at its base the collector potential of one transistor or the other of the differential transistor pair and to form an emitter follower circuit with the resistor selectively included therein. Thus, it is possible to prevent a malfunction of the ECl flip-flop circuit due to α-particles or the like.
Inventors
- 👤 Tohru Kobayashi
- 👤 Masato Hamamoto
- 👤 Toshio Yamada
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 15:41
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/26; H03K3/28; H03K3/281; H03K3/286; H03K3/288; H03K3/2885; H03K3/027; H03K3/037; H03K3/0375
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
213 words
A semiconductor integrated circuit device including a flip-flop circuit, said flip-flop circuit comprising: a first differential bipolar transistor; a second differential bipolar transistor coupled to said first differential bipolar transistor to form differential switching means; input means coupled to said first differential bipolar transistor for supplying the collector of said first differential bipolar transistor with a potential in accordance with input data; and feedback means coupled to said first and second differential bipolar transistors and including resistor means coupled in series between the respective bases of said first and second differential bipolar transistors, first bias means for supplying the base of said second differential bipolar transistor with a potential in accordance with a potential at the collector of said first differential bipolar transistor, second bias means for supplying the base of said first differential bipolar transistor with a potential in accordance with a potential at the collector of said second differential bipolar transistor, and first switching means coupled to the bases of said first and second differential bipolar transistors and to a predetermined potential point and for selectively coupling the base of either said first or second differential bipolar transistor to said predetermined potential point in accordance with a potential at the collector of each of said first and second differential bipolar transistors.
Claim 2
Dependent Claim
213 words
A semiconductor integrated circuit device including a flip-flop circuit, said flip-flop circuit comprising: a first differential bipolar transistor; a second differential bipolar transistor coupled to said first differential bipolar transistor to form differential switching means; input means coupled to said first differential bipolar transistor for supplying the collector of said first differential bipolar transistor with a potential in accordance with input data; and feedback means coupled to said first and second differential bipolar transistors and including resistor means coupled in series between the respective bases of said first and second differential bipolar transistors, first bias means for supplying the base of said second differential bipolar transistor with a potential in accordance with a potential at the collector of said first differential bipolar transistor, second bias means for supplying the base of said first differential bipolar transistor with a potential in accordance with a potential at the collector of said second differential bipolar transistor, and first switching means coupled to the bases of said first and second differential bipolar transistors and to a predetermined potential point and for selectively coupling the base of either said first or second differential bipolar transistor to said predetermined potential point in accordance with a potential at the collector of each of said first and second differential bipolar transistors.
Claim 3
Dependent Claim
80 words
A semiconductor integrated circuit device according to claim 1, wherein said first switching means includes second switching means for coupling the base of said second differential bipolar transistor to said predetermined potential point in accordance with a potential at the collector of said first differential bipolar transistor and third switching means for coupling the base of said first differential bipolar transistor to said predetermined potential point in accordance with a potential at the collector of said second differential bipolar transistor.
Claim 4
Dependent Claim
22 words
A semiconductor integrated circuit device according to claim 2, wherein each of said first and second bias means includes a bipolar transistor.
Claim 5
Dependent Claim
28 words
A semiconductor integrated circuit device according to claim 1, wherein said resistor means includes a resistor coupled between the bases of said first and second differential bipolar transistors.
Claim 6
Dependent Claim
28 words
A semiconductor integrated circuit device according to claim 4, further including a current circuit coupled to the emitters of said first and second differential bipolar transistors in common.
Claim 7
Dependent Claim
290 words
A semiconductor integrated circuit device including a first circuit for generating an output signal, first flip-flop means for generating a first flip-flop output signal according to said output signal from said first circuit, a second circuit for generating an output signal in accordance with said first flip-flop output signal, second flip-flop means for generating a second flip-flop output signal according to said output signal from said second circuit and a third circuit for receiving said second flip-flop output signal, at least one of said first and flip-flop means comprising: a first differential bipolar transistor; a second differential bipolar transistor coupled to said first differential bipolar transistor to form differential switching means; input means coupled to said first differential bipolar transistor for supplying the collector of said first differential bipolar transistor with a potential in accordance with said output signal; and feedback means coupled to said first and second differential bipolar transistors and including resistor means coupled in series between the respective bases of said first and second differential bipolar transistors, first bias means for supplying the base of said second differential bipolar transistor with a potential in accordance with a potential at the collector of said first differential bipolar transistor, second bias means for supplying the base of said first differential bipolar transistor with a potential in accordance with a potential at the collector of said second differential bipolar transistor, and first switching means coupled to the bases of said first and second differential bipolar transistors and to a predetermined potential point and for selectively coupling the base of either said first or second differential bipolar transistor to said predetermined potential point in accordance with a potential at the collector of each of said first and second differential bipolar transistors.
Claim 8
Dependent Claim
290 words
A semiconductor integrated circuit device including a first circuit for generating an output signal, first flip-flop means for generating a first flip-flop output signal according to said output signal from said first circuit, a second circuit for generating an output signal in accordance with said first flip-flop output signal, second flip-flop means for generating a second flip-flop output signal according to said output signal from said second circuit and a third circuit for receiving said second flip-flop output signal, at least one of said first and flip-flop means comprising: a first differential bipolar transistor; a second differential bipolar transistor coupled to said first differential bipolar transistor to form differential switching means; input means coupled to said first differential bipolar transistor for supplying the collector of said first differential bipolar transistor with a potential in accordance with said output signal; and feedback means coupled to said first and second differential bipolar transistors and including resistor means coupled in series between the respective bases of said first and second differential bipolar transistors, first bias means for supplying the base of said second differential bipolar transistor with a potential in accordance with a potential at the collector of said first differential bipolar transistor, second bias means for supplying the base of said first differential bipolar transistor with a potential in accordance with a potential at the collector of said second differential bipolar transistor, and first switching means coupled to the bases of said first and second differential bipolar transistors and to a predetermined potential point and for selectively coupling the base of either said first or second differential bipolar transistor to said predetermined potential point in accordance with a potential at the collector of each of said first and second differential bipolar transistors.
Claim 9
Dependent Claim
51 words
A semiconductor integrated circuit device according to claim 6, further comprising timing signal generating means for generating timing signals, wherein said input means includes means responsive to one of said timing signals for supplying the collector of said first differential bipolar transistor with a potential in accordance with said output signal.
Claim 10
Dependent Claim
28 words
A semiconductor integrated circuit device according to claim 7, wherein said resistor means includes a resistor coupled between the bases of said first and second differential bipolar transistors.
Claim 11
Dependent Claim
28 words
A semiconductor integrated circuit device according to claim 8, further including a current circuit coupled to the emitters of said first and second differential bipolar transistors in common.
Claim 12
Dependent Claim
80 words
A semiconductor integrated circuit device according to claim 9, wherein said first switching means includes second switching means for coupling the base of said second differential bipolar transistor to said predetermined potential point in accordance with a potential at the collector of said first differential bipolar transistor and third switching means for coupling the base of said first differential bipolar transistor to said predetermined potential point in accordance with a potential at the collector of said second differential bipolar transistor.
Claim 13
Dependent Claim
22 words
A semiconductor integrated circuit device according to claim 10, wherein each of said first and second bias means has a bipolar transistor.
Claim 14
Dependent Claim
55 words
A semiconductor integrated circuit device according to claim 11, wherein said input means includes first and second bipolar transistors coupled between said collector of said first differential bipolar transistor and a predetermined potential point, wherein said first bipolar transistor receives said output signal and said second bipolar transistor receives said one of said timing signals.
Claim 15
Dependent Claim
356 words
A semiconductor integrated circuit device including a first circuit for generating an output signal, first flip-flop means for generating a first flip-flop output signal according to said output signal from said first circuit, a second circuit for generating an output signal in accordance with said first flip-flop output signal, second flip-flop means for generating a second flip-flop output signal according to said output signal from said second circuit and a third circuit for receiving said second flip-flop output signal, at least one of said first and flip-flop means comprising: a first differential bipolar transistor; a second differential bipolar transistor coupled to said first differential bipolar transistor to form a differential switching means in combination with said first differential bipolar transistor; input means coupled to said first differential bipolar transistor to supply the collector of said first differential bipolar transistor with a potential in accordance with said output signal; and feedback means coupled to said first and second differential bipolar transistors to feed back a potential corresponding to a potential at the collector of said first differential bipolar transistor to the base of said second differential bipolar transistor and also to feed back a potential corresponding to a potential at the collector of said second differential bipolar transistor to the base of said first differential bipolar transistor, wherein said feedback means includes resistor means coupled in series between the respective bases of said first and second differential bipolar transistors, first bias means for supplying the base of said second differential bipolar transistor with a potential in accordance with a potential at the collector of said first differential bipolar transistor, second bias means for supplying the base of said first differential bipolar transistor with a potential in accordance with a potential at the collector of said second differential bipolar transistor, and first switching means coupled to the bases of said first and second differential bipolar transistors and a predetermined potential point to couple selectively the base of either said first or second differential bipolar transistor to said predetermined potential point in accordance with a potential at the collector of each of said first and second differential bipolar transistors.
Claim 16
Dependent Claim
356 words
A semiconductor integrated circuit device including a first circuit for generating an output signal, first flip-flop means for generating a first flip-flop output signal according to said output signal from said first circuit, a second circuit for generating an output signal in accordance with said first flip-flop output signal, second flip-flop means for generating a second flip-flop output signal according to said output signal from said second circuit and a third circuit for receiving said second flip-flop output signal, at least one of said first and flip-flop means comprising: a first differential bipolar transistor; a second differential bipolar transistor coupled to said first differential bipolar transistor to form a differential switching means in combination with said first differential bipolar transistor; input means coupled to said first differential bipolar transistor to supply the collector of said first differential bipolar transistor with a potential in accordance with said output signal; and feedback means coupled to said first and second differential bipolar transistors to feed back a potential corresponding to a potential at the collector of said first differential bipolar transistor to the base of said second differential bipolar transistor and also to feed back a potential corresponding to a potential at the collector of said second differential bipolar transistor to the base of said first differential bipolar transistor, wherein said feedback means includes resistor means coupled in series between the respective bases of said first and second differential bipolar transistors, first bias means for supplying the base of said second differential bipolar transistor with a potential in accordance with a potential at the collector of said first differential bipolar transistor, second bias means for supplying the base of said first differential bipolar transistor with a potential in accordance with a potential at the collector of said second differential bipolar transistor, and first switching means coupled to the bases of said first and second differential bipolar transistors and a predetermined potential point to couple selectively the base of either said first or second differential bipolar transistor to said predetermined potential point in accordance with a potential at the collector of each of said first and second differential bipolar transistors.
Claim 17
Dependent Claim
51 words
A semiconductor integrated circuit device according to claim 13, further comprising timing signal generating means for generating timing signals, wherein said input means incudes means responsive to one of said timing signals for supplying the collector of said first differential bipolar transistor with a potential in accordance with said output signal.
Claim 18
Dependent Claim
28 words
A semiconductor integrated circuit device according to claim 14, wherein said resistor means includes a resistor coupled between the bases of said first and second differential bipolar transistors.
Claim 19
Dependent Claim
536 words
A semiconductor integrated circuit device including timing signal generating means for generating first and second timing signals which are different from each other, a first circuit for generating an output signal, first flip-flop means responsive to said first timing signal for generating a first flip-flop output signal in accordance with said output signal from said first circuit, a second circuit for generating an output signal in accordance with said first flip-flop output signal, second flip-flop means responsive to said timing signal for generating a second flip-flop output signal in accordance with said output signal from said second circuit and a third circuit for receiving said second flip-flop output signal, wherein said first flip-flop means includes: a first differential bipolar transistor; a second differential bipolar transistor coupled to said first differential bipolar transistor to form differential switching means; input means coupled to said first differential bipolar transistor responsive to said first timing signal for supplying the collector of said first differential bipolar transistor with a potential in accordance with said output signal; and feedback means coupled to said first and second differential bipolar transistors and including resistor means coupled in series between the respective bases of said first and second differential bipolar transistors, first bias means for supplying the base of said second differential bipolar transistor with a potential in accordance with a potential at the collector of said first differential bipolar transistor, second bias means for supplying the base of said first differential bipolar transistor with a potential in accordance with a potential at the collector of said second differential bipolar transistor, and first switching means coupled to the bases of said first and second differential bipolar transistors and to a predetermined potential point and for selectively coupling the base of either said first or second differential bipolar transistor to said predetermined potential point in accordance with a potential at the collector of each of said first and second differential bipolar transistors, and wherein said second flip-flop means includes: a first differential bipolar transistor; a second differential bipolar transistor coupled to said first differential bipolar transistor to form differential switching means; input means coupled to said first differential bipolar transistor responsive to said second timing signal for supplying the collector of said first differential bipolar transistor with a potential in accordance with said output signal; and feedback means coupled to said first and second differential bipolar transistors and including resistor means coupled in series between the respective bases of said first and second differential bipolar transistors, first bias means for supplying the base of said second differential bipolar transistor with a potential in accordance with a potential at the collector of said first differential bipolar transistor, second bias means for supplying the base of said first differential bipolar transistor with a potential in accordance with a potential at the collector of said second differential bipolar transistor, and first switching means coupled to the bases of said first and second differential bipolar transistors and to a predetermined potential point and for selectively coupling the base of either said first or second differential bipolar transistor to said predetermined potential point in accordance with a potential at the collector of each of said first and second differential bipolar transistors.
Claim 20
Dependent Claim
536 words
A semiconductor integrated circuit device including timing signal generating means for generating first and second timing signals which are different from each other, a first circuit for generating an output signal, first flip-flop means responsive to said first timing signal for generating a first flip-flop output signal in accordance with said output signal from said first circuit, a second circuit for generating an output signal in accordance with said first flip-flop output signal, second flip-flop means responsive to said timing signal for generating a second flip-flop output signal in accordance with said output signal from said second circuit and a third circuit for receiving said second flip-flop output signal, wherein said first flip-flop means includes: a first differential bipolar transistor; a second differential bipolar transistor coupled to said first differential bipolar transistor to form differential switching means; input means coupled to said first differential bipolar transistor responsive to said first timing signal for supplying the collector of said first differential bipolar transistor with a potential in accordance with said output signal; and feedback means coupled to said first and second differential bipolar transistors and including resistor means coupled in series between the respective bases of said first and second differential bipolar transistors, first bias means for supplying the base of said second differential bipolar transistor with a potential in accordance with a potential at the collector of said first differential bipolar transistor, second bias means for supplying the base of said first differential bipolar transistor with a potential in accordance with a potential at the collector of said second differential bipolar transistor, and first switching means coupled to the bases of said first and second differential bipolar transistors and to a predetermined potential point and for selectively coupling the base of either said first or second differential bipolar transistor to said predetermined potential point in accordance with a potential at the collector of each of said first and second differential bipolar transistors, and wherein said second flip-flop means includes: a first differential bipolar transistor; a second differential bipolar transistor coupled to said first differential bipolar transistor to form differential switching means; input means coupled to said first differential bipolar transistor responsive to said second timing signal for supplying the collector of said first differential bipolar transistor with a potential in accordance with said output signal; and feedback means coupled to said first and second differential bipolar transistors and including resistor means coupled in series between the respective bases of said first and second differential bipolar transistors, first bias means for supplying the base of said second differential bipolar transistor with a potential in accordance with a potential at the collector of said first differential bipolar transistor, second bias means for supplying the base of said first differential bipolar transistor with a potential in accordance with a potential at the collector of said second differential bipolar transistor, and first switching means coupled to the bases of said first and second differential bipolar transistors and to a predetermined potential point and for selectively coupling the base of either said first or second differential bipolar transistor to said predetermined potential point in accordance with a potential at the collector of each of said first and second differential bipolar transistors.
Claim 21
Dependent Claim
37 words
A semiconductor integrated circuit device according to claim 16, wherein each of said resistor means in said first and second flip-flop means includes a resistor coupled between the bases of said first and second differential bipolar transistors.
Claim 22
Dependent Claim
37 words
A semiconductor integrated circuit device according to claim 17, wherein each of said first and second flip-flop means further includes a current circuit coupled to the emitters of said first and second differential bipolar transistors in common.
Claim 23
Dependent Claim
89 words
A semiconductor integrated circuit device according to claim 18, wherein each of said first switching means in said first and second flip-flop means includes second switching means for coupling the base of said second differential bipolar transistor to said predetermined potential point in accordance with a potential at the collector of said first differential bipolar transistor and third switching means for coupling the base of said first differential bipolar transistor to said predetermined potential point in accordance with a potential at the collector of said second differential bipolar transistor.
Claim 24
Dependent Claim
29 words
A semiconductor integrated circuit device according to claim 19, wherein each of said first and second bias means in said first and second flip-flop means includes a bipolar transistor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-07-09 | 1994-01-08 | 1994-07-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-07-09 | 1998-01-08 | 1998-07-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-07-09 | 2002-01-08 | 2002-07-10 | $7700.00 | Window Closed / Lapsed |