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US4939696A
Expired / Lapsed
US
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Semiconductor memory device
Assignee: Hitachi Ltd
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Filing: 1988-07-28
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Granted: 1990-07-03
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Expires: 2008-07-28
Abstract
Abstract A semiconductor memory device comprising a decoder circuit for selecting one divided word line from among a plurality of divided word lines; the decoder circuit including a first drive MOSFET which is arranged so as to be shared by a plurality of memory blocks each having the divided word lines with memory cells respectively coupled thereto and which receives signals to be supplied to main word lines, second drive MOSFETs which are respectively coupled to the first MOSFET in series so as to share it and which receive respective predecode signals corresponding to the plurality of divided word lines, a plurality of load means which are respectively coupled to drains of the second drive MOSFETs, and inverter circuits which invert phases of drain output signals of the respective second drive MOSFETs and transmit the inverted signals to the corresponding divided word lines.
Inventors
- 👤 Sasaki Katsuo
- 👤 Toyoshima Hiroshi
- 👤 Hanamura Shoji
- 👤 Kubotera Masaaki
- 👤 Komiyazi Kunihiro
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 05:34
CPC Classifications
G; G11; G11C; G11C7/00; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/413; G11C11/417; G11C11/418
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
170 words
A semiconductor memory device comprising: a plurality of memory blocks each of which includes a plurality of word lines having memory cells coupled thereto, respectively, a select signal line which is connected to said plurality of memory blocks, first selection means coupled to said plurality of word lines and said select signal line, and for selecting at least one word line from among said plurality of word lines, and second selection means coupled to said select signal line and said first selection means, and for supplying select signals thereto, wherein said first selection means includes first variable resistance means having its conductivity varied by the select signal from said select signal line, a plurality of load means, a plurality of second variable resistance means coupled between the respective load means and said first variable resistance means and having their conductivities varied by the select signals supplied from said second selection means, and a plurality of coupling means coupled between said second variable resistance means and said plurality of word lines.
Claim 2
Dependent Claim
170 words
A semiconductor memory device comprising: a plurality of memory blocks each of which includes a plurality of word lines having memory cells coupled thereto, respectively, a select signal line which is connected to said plurality of memory blocks, first selection means coupled to said plurality of word lines and said select signal line, and for selecting at least one word line from among said plurality of word lines, and second selection means coupled to said select signal line and said first selection means, and for supplying select signals thereto, wherein said first selection means includes first variable resistance means having its conductivity varied by the select signal from said select signal line, a plurality of load means, a plurality of second variable resistance means coupled between the respective load means and said first variable resistance means and having their conductivities varied by the select signals supplied from said second selection means, and a plurality of coupling means coupled between said second variable resistance means and said plurality of word lines.
Claim 3
Dependent Claim
61 words
A semiconductor memory device according to claim 1, wherein said first variable resistance means is constructed of a MISFET of one conductivity type, each of said second variable resistance means is constructed of a MISFET of said one conductivity type, and each of said load means is constructed of a MISFET of a conductivity type opposite to said one conductivity type.
Claim 4
Dependent Claim
18 words
A semiconductor memory device according to claim 2, wherein each of said coupling means is phase inversion means.
Claim 5
Dependent Claim
17 words
A semiconductor memory device according to claim 3, wherein said phase inversion means is an inverter circuit.
Claim 6
Dependent Claim
18 words
A semiconductor memory device according to claim 4, wherein each of said memory cells includes a flip-flop circuit.
Claim 7
Dependent Claim
117 words
A semiconductor memory device comprising a plurality of memory blocks each of which includes divided word lines having memory cells coupled thereto, respectively, and a plurality of word decoder circuits each of which includes a first drive MOSFET receiving a signal of a main word line, second drive MOSFETs, the source of each of said second drive MOSFET, connected to the drain of said first drive MOSFET, each second drive MOSFET receiving a predecode signal corresponding to a divided word line, respectively, a plurality of load means connected to drains of the respective second drive MOSFETs, and inverter circuits receiving drain outputs of the respective second drive MOSFETs so as to drive the corresponding divided word lines.
Claim 8
Dependent Claim
117 words
A semiconductor memory device comprising a plurality of memory blocks each of which includes divided word lines having memory cells coupled thereto, respectively, and a plurality of word decoder circuits each of which includes a first drive MOSFET receiving a signal of a main word line, second drive MOSFETs, the source of each of said second drive MOSFET, connected to the drain of said first drive MOSFET, each second drive MOSFET receiving a predecode signal corresponding to a divided word line, respectively, a plurality of load means connected to drains of the respective second drive MOSFETs, and inverter circuits receiving drain outputs of the respective second drive MOSFETs so as to drive the corresponding divided word lines.
Claim 9
Dependent Claim
76 words
A semiconductor memory device according to claim 6, wherein two of said word decoder circuits are arranged between one pair of memory blocks among said plurality of memory blocks, said first drive MOSFET drain is connected to the source output of each said second decode circuit second drive MOSFET, and said second drive MOSFETs of each of said two word decoder circuits receive the predecode signals corresponding to either of the right and left memory blocks.
Claim 10
Dependent Claim
42 words
A semiconductor memory device according to claim 7, wherein said drive MOSFETs which constitute said each word decoder circuit are N-channel MOSFETs, and said plurality of load means are respectively made of P-channel MOSFETs which are steadily brought into "on" states thereof.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-07-02 | 1994-01-01 | 1994-07-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-07-02 | 1998-01-01 | 1998-07-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-07-02 | 2002-01-01 | 2002-07-03 | $7700.00 | Window Closed / Lapsed |