US4393472A
Expired / Lapsed
US
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Semiconductor memory circuit
Assignee: Fujitsu Ltd
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Filing: 1980-12-18
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Granted: 1983-07-12
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Expires: 2000-12-18
Abstract
Abstract A semiconductor memory circuit is provided with a right memory cell group and a left memory cell group, word decoders corresponding to respective rows and; which are located between the right and left memory cell groups and which specify an address in the word direction of these memory cell groups, and column decoders corresponding to respective column which specify an address in the bit direction of these memory cell groups. The memory circuit also includes right and left memory cell group selection and drive gates for every word decoder and circuits for detecting whether the accessed memory cell is in the right or left memory cell group. The right or left memory cell group selection and drive gates operate in a complimentary manner and in accordance with the accessed memory cell being in the right or left memory cell group.
Inventors
- 👤 Hiroshi Shimada
- 👤 Keizo Aoyama
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 07:35
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/412; G11C11/413; G11C11/417; G11C11/418; G11C5/00; G11C5/02; G11C5/025; G11C8/00; G11C8/12
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
225 words
A semiconductor memory circuit comprising: a right memory cell group and a left memory cell group, each having a plurality of rows and columns corresponding to word lines and bit lines, respectively; a plurality of word decoders respectively connected to corresponding ones of said rows, said word decoders being connected between the right and left memory cell groups and receiving row address signals specifying a word line within the memory cell group to be selected; and a plurality of column decoders correspondingly connected to respective ones of said columns for receiving column address signals specifying the bit within the memory cell group to be selected; a plurality of right memory cell group selection and drive gates operatively connected between respective ones of said word decoders and respective ones of said rows connected to said right memory cell group; a plurality of left memory cell group selection and drive gates operatively connected between respective ones of said word decoders and respective ones of said rows connected to said left memory cell group; and discriminating means for discriminating whether the memory cell to be selected is located in the right or left memory cell group, for providing an output responsive to said discriminating means, and for controlling the right and left memory cell group selection and drive gates in accordance with the output of said discriminating means.
Claim 2
Dependent Claim
225 words
A semiconductor memory circuit comprising: a right memory cell group and a left memory cell group, each having a plurality of rows and columns corresponding to word lines and bit lines, respectively; a plurality of word decoders respectively connected to corresponding ones of said rows, said word decoders being connected between the right and left memory cell groups and receiving row address signals specifying a word line within the memory cell group to be selected; and a plurality of column decoders correspondingly connected to respective ones of said columns for receiving column address signals specifying the bit within the memory cell group to be selected; a plurality of right memory cell group selection and drive gates operatively connected between respective ones of said word decoders and respective ones of said rows connected to said right memory cell group; a plurality of left memory cell group selection and drive gates operatively connected between respective ones of said word decoders and respective ones of said rows connected to said left memory cell group; and discriminating means for discriminating whether the memory cell to be selected is located in the right or left memory cell group, for providing an output responsive to said discriminating means, and for controlling the right and left memory cell group selection and drive gates in accordance with the output of said discriminating means.
Claim 3
Dependent Claim
19 words
A semiconductor memory circuit according to claim 1, wherein the discriminating output corresponds to a specified column address signal.
Claim 4
Dependent Claim
42 words
A semiconductor memory circuit according to claim 1, wherein each of the plurality of right and the plurality of left memory cell group selection and drive gates comprises a series transistor connected in series with said respective ones of said word lines.
Claim 5
Dependent Claim
32 words
A semiconductor memory circuit according to claim 3, further comprising a transistor for preventing a floating condition of said respective ones of said word lines connected in parallel with said series transistor.
Claim 6
Dependent Claim
22 words
A semiconductor memory circuit according to claim 1, wherein said word decoders are located between the right and left memory cell groups.
Claim 7
Dependent Claim
17 words
A semiconductor memory circuit according to claim 1, wherein said memory cell groups comprise flip-flop memory cells.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-07-11 | 1987-01-10 | 1987-07-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-07-11 | 1991-01-10 | 1991-07-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-07-11 | 1995-01-10 | 1995-07-12 | $7700.00 | Window Closed / Lapsed |