US4290120A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Circuit arrangement for reading out and regenerating items of information stored in one-transistor storage elements
Assignee: Siemens AG
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Filing: 1979-08-23
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Granted: 1981-09-15
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Expires: 1999-08-23
Abstract
Abstract A circuit arrangement is disclosed for reading out and regenerating items of information stored in one-transistor storage elements. For read-out, storage elements addressed by the activation of a word line transfer an existing information charge into assigned bit lines, and wherein the bit lines influence inputs of assigned read-out/regenerating amplifiers. The storage density of semiconductor stores is increased by providing a circuit arrangement in which the disproportion in terms of area between technologically realizable storage matrices and the required amplifiers which is a by-product of the miniaturization of stores of the above mentioned type does not occur. A group of m bit lines are in each case combined to form groups and are consecutively connected via a multiplexer to a common read-out/regenerating amplifier.
Inventors
- 👤 Karl U. Stein
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 20:15
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/406
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
238 words
A circuit arrangement for reading out and regenerating items of information stored in one-transistor storage elements, comprising: a plurality of word lines and bit lines; storage element means addressed by the activation of a word line during read-out for transferring an existing information charge into assigned bit lines; said assigned bit lines being connected to influence inputs of assigned read-out/regenerating amplifiers; m bit lines in each case being combined as line groups (1, 2 . . . m; m+1, m+2, . . . 2m; (p-1) m+1, (p-1) m+2 . . . pm); each of said bit line groups being assigned to a multiplexer; individual bit lines of a bit line group being connected to individual inputs of the assigned multiplexer; the assigned multiplexers each being connected by one output to the input of an assigned read-out/regenerating amplifier; a multiplex decoder means for consecutively connecting all the individual bit lines of each bit line group in a predetermined sequence via the relevant multiplexer to the input of the assigned read-out/regenerating amplifier; and, in order to improve the transfer of charge into the bit lines, threshold transistors are connected in pairs by their gates to relevant outputs of the multiplex decoder means, the threshold transistors forming means for switching individual inputs of the multiplexer; and for each output of the multiplex decoder means a load element being provided whose second terminal is in each case connected to a threshold potential.
Claim 2
Dependent Claim
238 words
A circuit arrangement for reading out and regenerating items of information stored in one-transistor storage elements, comprising: a plurality of word lines and bit lines; storage element means addressed by the activation of a word line during read-out for transferring an existing information charge into assigned bit lines; said assigned bit lines being connected to influence inputs of assigned read-out/regenerating amplifiers; m bit lines in each case being combined as line groups (1, 2 . . . m; m+1, m+2, . . . 2m; (p-1) m+1, (p-1) m+2 . . . pm); each of said bit line groups being assigned to a multiplexer; individual bit lines of a bit line group being connected to individual inputs of the assigned multiplexer; the assigned multiplexers each being connected by one output to the input of an assigned read-out/regenerating amplifier; a multiplex decoder means for consecutively connecting all the individual bit lines of each bit line group in a predetermined sequence via the relevant multiplexer to the input of the assigned read-out/regenerating amplifier; and, in order to improve the transfer of charge into the bit lines, threshold transistors are connected in pairs by their gates to relevant outputs of the multiplex decoder means, the threshold transistors forming means for switching individual inputs of the multiplexer; and for each output of the multiplex decoder means a load element being provided whose second terminal is in each case connected to a threshold potential.
Claim 3
Dependent Claim
154 words
A circuit arrangement for reading out and regenerating items of information stored in one-transistor storage elements, comprising: a plurality of storage elements addressed by a plurality of word lines and bit lines; the bit lines being formed into bit line groups and each bit line group connecting to a multiplexer; each multiplexer connecting to a read-out regenerating amplifier; multiplex decoder means connecting to each of the multiplexers for consecutively connecting each of the bit lines within a given bit line group to its assigned read-out/regenerating amplifier; and, in order to improve the transfer of charge into the bit lines, threshold transistors are connected in pairs by their gates to relevant outputs of the multiplex decoder means, the threshold transistors forming means for switching individual inputs of the multiplexer; and for each output of the multiplex decoder means a load element being provided whose second terminal is in each case connected to a threshold potential.
Claim 4
Dependent Claim
154 words
A circuit arrangement for reading out and regenerating items of information stored in one-transistor storage elements, comprising: a plurality of storage elements addressed by a plurality of word lines and bit lines; the bit lines being formed into bit line groups and each bit line group connecting to a multiplexer; each multiplexer connecting to a read-out regenerating amplifier; multiplex decoder means connecting to each of the multiplexers for consecutively connecting each of the bit lines within a given bit line group to its assigned read-out/regenerating amplifier; and, in order to improve the transfer of charge into the bit lines, threshold transistors are connected in pairs by their gates to relevant outputs of the multiplex decoder means, the threshold transistors forming means for switching individual inputs of the multiplexer; and for each output of the multiplex decoder means a load element being provided whose second terminal is in each case connected to a threshold potential.
References Cited (Backward Citations)
DE2309192C3
Cited
US4160275A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-09-14 | 1985-03-16 | 1985-09-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-09-14 | 1989-03-16 | 1989-09-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-09-14 | 1993-03-16 | 1993-09-15 | $7700.00 | Window Closed / Lapsed |