US4937738A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Data processing system which selectively bypasses a cache memory in fetching information based upon bit information of an instruction
Assignee: Hitachi Microcomputer System Ltd
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Filing: 1985-08-23
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Granted: 1990-06-26
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Expires: 2005-08-23
Abstract
Abstract A cache memory contained in a processor features a high efficiency in spite of its small capacity. In the cache memory control circuit, it is detected whether the access operation of the processor is directed to a particular region of the memory, and when the data is to be read out from, or is to be written onto, the particular region, the data is copied onto the cache memory and when the data is to be read out from other regions, operation of the memory is executed immediately without waiting for the reference of cache memory. By assigning the particular region for the data that is to be used repeatedly, it is possible to provide a cache memory having good efficiency in spite of its small capacity. A representative example of such data is the data in a stack.
Inventors
- 👤 Kunio Uchiyama
- 👤 Atsushi Hasegawa
- 👤 Takeshi Aimoto
- 👤 Tadahiko Nishimukai
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 18:33
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0888
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
302 words
A data processing system comprising: a main memory for storing data; a microprocessor coupled to said main memory and including a cache memory, the cache memory having a capacity smaller than that of said main memory and operating at a speed faster than that of said main memory, said cache memory being accessed by receipt of addresses and holding a copy of a part of said data stored at locations corresponding to said addresses in said main memory; wherein said microprocessor further includes a frame pointer for designating an address of a current frame which is accessed during execution of a subroutine, said current frame being in a stack of said data stored in said main memory, and a stack pointer for designating an address of the top of said stack; wherein instructions are stored in said main memory and executed by said microprocessor, at least some instructions for said microprocessor include bit information which designates whether said instruction calls or does not call for accessing a stack area designated by said frame pointer and said stack pointer; wherein said microprocessor further includes: (1) first means for detecting said bit information in an instruction; and (2) second means for accessing said cache memory to read out said copy of said part of said data from said cache memory before accessing said main memory in response to a detection result of said first means in case said bit information designates that said instruction calls for accessing said stack area; and wherein said second means accesses said main memory to read out a part of said data from said main memory without regard to said cache memory in response to another detection result of said first means in case said bit information designates that said instruction does not call for accessing said stack area.
Claim 2
Dependent Claim
302 words
A data processing system comprising: a main memory for storing data; a microprocessor coupled to said main memory and including a cache memory, the cache memory having a capacity smaller than that of said main memory and operating at a speed faster than that of said main memory, said cache memory being accessed by receipt of addresses and holding a copy of a part of said data stored at locations corresponding to said addresses in said main memory; wherein said microprocessor further includes a frame pointer for designating an address of a current frame which is accessed during execution of a subroutine, said current frame being in a stack of said data stored in said main memory, and a stack pointer for designating an address of the top of said stack; wherein instructions are stored in said main memory and executed by said microprocessor, at least some instructions for said microprocessor include bit information which designates whether said instruction calls or does not call for accessing a stack area designated by said frame pointer and said stack pointer; wherein said microprocessor further includes: (1) first means for detecting said bit information in an instruction; and (2) second means for accessing said cache memory to read out said copy of said part of said data from said cache memory before accessing said main memory in response to a detection result of said first means in case said bit information designates that said instruction calls for accessing said stack area; and wherein said second means accesses said main memory to read out a part of said data from said main memory without regard to said cache memory in response to another detection result of said first means in case said bit information designates that said instruction does not call for accessing said stack area.
Claim 3
Dependent Claim
21 words
A data processing system according to claim 3, wherein said cache memory is formed on a single chip of said microprocessor.
Claim 4
Dependent Claim
17 words
A data processing system according to claim 4, wherein said main memory is disposed outside said microprocessor.
Claim 5
Dependent Claim
296 words
A microprocessor for use with a main memory in a data processing system, said microprocessor comprising: a cache memory, the cache memory having a capacity smaller than that of said main memory and operating at a speed faster than that of said main memory, said cache memory being accessed by receipt of addresses and holding a copy of a part of data stored at locations corresponding to said addresses in said main memory; a frame pointer for designating an address of a current frame which is accessed during a subroutine's execution, said current frame being in a stack of said data stored in said main memory; and a stack pointer for designating an address of the top of said stack; wherein instructions are stored in said main memory and executed by said microprocessor, at least some instructions for said microprocessor include bit information which designates whether said instruction calls or does not call for accessing a stack area designated by said frame pointer and said stack pointer; and wherein said microprocessor further includes: (1) first means for detecting said bit information in an instruction; and (2) second means coupled to said cache memory for accessing said cache memory to read out said copy of said part of said data from said cache memory before accessing said main memory for said data in response to a detection result of said first means in case said bit information designates that said instruction calls for accessing said stack area; and wherein said second means accesses said main memory to read out data from said main memory without regard to said cache memory in response to another detection result of said first means in case said bit information designates that said instruction does not call for accessing said stack area.
Claim 6
Dependent Claim
296 words
A microprocessor for use with a main memory in a data processing system, said microprocessor comprising: a cache memory, the cache memory having a capacity smaller than that of said main memory and operating at a speed faster than that of said main memory, said cache memory being accessed by receipt of addresses and holding a copy of a part of data stored at locations corresponding to said addresses in said main memory; a frame pointer for designating an address of a current frame which is accessed during a subroutine's execution, said current frame being in a stack of said data stored in said main memory; and a stack pointer for designating an address of the top of said stack; wherein instructions are stored in said main memory and executed by said microprocessor, at least some instructions for said microprocessor include bit information which designates whether said instruction calls or does not call for accessing a stack area designated by said frame pointer and said stack pointer; and wherein said microprocessor further includes: (1) first means for detecting said bit information in an instruction; and (2) second means coupled to said cache memory for accessing said cache memory to read out said copy of said part of said data from said cache memory before accessing said main memory for said data in response to a detection result of said first means in case said bit information designates that said instruction calls for accessing said stack area; and wherein said second means accesses said main memory to read out data from said main memory without regard to said cache memory in response to another detection result of said first means in case said bit information designates that said instruction does not call for accessing said stack area.
Claim 7
Dependent Claim
19 words
A microprocessor according to claim 4, wherein said cache memory is formed ON a single chip of said microprocessor.
Claim 8
Dependent Claim
261 words
A microprocessor for use with a main memory in a data processing system, said microprocessor comprising: a cache memory, the cache memory having a capacity smaller than that of said main memory and an operating speed faster than that of said main memory, said cache memory being accessed by receipt of addresses and holding a copy of a part of data stored at locations corresponding to said addresses in said main memory; wherein instructions stored in said main memory are accessed and executed by said microprocessor, and at least some instructions for said microprocessor include bit information which designates whether the instruction including said bit information accesses or does not access a stack in said main memory for storing information for a subroutine, said stack being repeatedly accessed at a high probability rate; wherein said microprocessor further includes: (1) first means for detecting said bit information in an instruction; and (2) second means coupled to said cache memory for accessing said cache memory to read out said copy of said part of said data from said cache memory before accessing said main memory for said data in response to a detection result of said first means in case said bit information designates that said instruction calls for accessing said stack area; and wherein said second means accesses said main memory to read out data from said main memory without regard to said cache memory in response to another detection result of said first means in case said bit information designates that said instruction does not call for accessing said stack area.
Claim 9
Dependent Claim
261 words
A microprocessor for use with a main memory in a data processing system, said microprocessor comprising: a cache memory, the cache memory having a capacity smaller than that of said main memory and an operating speed faster than that of said main memory, said cache memory being accessed by receipt of addresses and holding a copy of a part of data stored at locations corresponding to said addresses in said main memory; wherein instructions stored in said main memory are accessed and executed by said microprocessor, and at least some instructions for said microprocessor include bit information which designates whether the instruction including said bit information accesses or does not access a stack in said main memory for storing information for a subroutine, said stack being repeatedly accessed at a high probability rate; wherein said microprocessor further includes: (1) first means for detecting said bit information in an instruction; and (2) second means coupled to said cache memory for accessing said cache memory to read out said copy of said part of said data from said cache memory before accessing said main memory for said data in response to a detection result of said first means in case said bit information designates that said instruction calls for accessing said stack area; and wherein said second means accesses said main memory to read out data from said main memory without regard to said cache memory in response to another detection result of said first means in case said bit information designates that said instruction does not call for accessing said stack area.
Claim 10
Dependent Claim
19 words
A microprocessor according to claim 6, wherein said cache memory is formed on a single chip of said microprocessor.
Claim 11
Dependent Claim
254 words
A microprocessor for use with a main memory in a data processing system, said microprocessor comprising: a cache memory, the cache memory having a capacity smaller than that of said main memory and an operating speed faster than that of said main memory, said cache memory being accessed by receipt of addresses and holding a copy of a part of data stored at locations corresponding to said addresses in said main memory; wherein instructions stored in said main memory are accessed and executed by said microprocessor, and at least some instructions for said microprocessor include bit information which designates whether said instruction calls or does not call for accessing a data area in said main memory which is repeatedly accessed at a high probability rate; wherein said microprocessor further includes (1) first means for detecting said bit information in an instruction; and (2) second means coupled to said cache memory for accessing said cache memory and reading out said copy of said part of said data from said cache memory instead of accessing said main memory for said data in response to a detection result of said first means indicating that said bit information designates an instruction which calls for accessing said data area; and wherein said second means accesses said main memory and reads out data from said main memory without regard to said cache memory in response to another detection result of said first means indicating that said bit information designates an instruction which does not call for accessing said data area.
Claim 12
Dependent Claim
254 words
A microprocessor for use with a main memory in a data processing system, said microprocessor comprising: a cache memory, the cache memory having a capacity smaller than that of said main memory and an operating speed faster than that of said main memory, said cache memory being accessed by receipt of addresses and holding a copy of a part of data stored at locations corresponding to said addresses in said main memory; wherein instructions stored in said main memory are accessed and executed by said microprocessor, and at least some instructions for said microprocessor include bit information which designates whether said instruction calls or does not call for accessing a data area in said main memory which is repeatedly accessed at a high probability rate; wherein said microprocessor further includes (1) first means for detecting said bit information in an instruction; and (2) second means coupled to said cache memory for accessing said cache memory and reading out said copy of said part of said data from said cache memory instead of accessing said main memory for said data in response to a detection result of said first means indicating that said bit information designates an instruction which calls for accessing said data area; and wherein said second means accesses said main memory and reads out data from said main memory without regard to said cache memory in response to another detection result of said first means indicating that said bit information designates an instruction which does not call for accessing said data area.
Claim 13
Dependent Claim
19 words
A microprocessor according to claim 8, wherein said cache memory is formed on a single chip of said microprocessor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-06-25 | 1993-12-25 | 1994-06-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-06-25 | 1997-12-25 | 1998-06-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-06-25 | 2001-12-25 | 2002-06-26 | $7700.00 | Window Closed / Lapsed |