Semiconductor memory device suitable for use as a dot image buffer for a printer

Claim 2

A semiconductor memory, comprising: a memory cell array constituted by a plurality of rowwise lines and a plurality of columnwise lines; decoder means for selecting one rowwise line of said memory cell array; first selecting means connected to said memory cell array for selecting a first group from a plurality of groups into which bits of said selected rowwise line are divided, said first group representing a series of bits arranged in parallel to the rowwise lines; second selecting means connected to said memory cell array for selecting one bit at a bit position from every one of said plurality of bit groups to thereby form a second group which represents a series of bits arranged in parallel to the columnwise lines; and third selecting means responsive to a rotation signal, for selecting one group from said first and second groups obtained through said first and second selecting means.

Claim 3

A semiconductor memory according to claim 1, wherein the number of bits contained in said first group obtained through said first selecting means is equal to the number of bits contained in said second group obtained through said second selecting means.

Claim 4

A semiconductor memory according to claim 1, wherein when the bits of said selected one rowwise line are to be represented in the form of a matrix array, said first group obtained through said first selecting means corresponds to one row of said matrix array while said second group obtained through said second selecting means corresponds to one column of said matrix array.

Claim 5

A semiconductor memory according to claim 1, wherein said first, second and third selecting means are bidirectional.

Claim 6

A semiconductor memory according to claim 1, wherein said decoder means has an input supplied with an address signal.

Claim 7

A semiconductor memory according to claim 1, wherein said decoder means includes counter means.

Claim 8

A semiconductor memory, comprising: a memory cell array constituted by a plurality of rowwise lines and a plurality of columnwise lines; first polarity control means for selectively inverting a part of an input address signal; first decoder means connected to said first polarity control means for selecting one rowwise line of said memory cell array; first selecting means connected to said memory cell array for selecting one group from a plurality of groups into which the bits of said selected one rowwise line are divided; second selecting means connected to said memory cell array for selecting one bit from every one of said plurality of groups for thereby forming one group; second decoder means responding to said remaining part of said input address signal to designate two groups obtained through each of said first and second selecting means; third selecting means for selecting one of the two groups obtained through said first and second selecting means; sequence control means connected to said third selecting means for controlling the bit sequence direction of said one group selected by said third selecting means; and mode selecting means connected to said first polarity control means, said third selecting means and said sequence control means for controlling these means to rotate the written bits on the 90° basis.

Claim 9

A semiconductor memory, comprising: a memory cell array constituted by a plurality of rowwise lines and a plurality of columnwise lines; first polarity control means for selectively inverting a part of an input address signal; first decoder means connected to said first polarity control means for selecting one rowwise line of said memory cell array; first selecting means connected to said memory cell array for selecting one group from a plurality of groups into which the bits of said selected one rowwise line are divided; second selecting means connected to said memory cell array for selecting one bit from every one of said plurality of groups for thereby forming one group; second decoder means responding to said remaining part of said input address signal to designate two groups obtained through each of said first and second selecting means; third selecting means for selecting one of the two groups obtained through said first and second selecting means; sequence control means connected to said third selecting means for controlling the bit sequence direction of said one group selected by said third selecting means; and mode selecting means connected to said first polarity control means, said third selecting means and said sequence control means for controlling these means to rotate the written bits on the 90° basis.

Claim 10

A semiconductor memory according to claim 7, further comprising second polarity control means connected to said second decoder means and said mode selecting means for responding to the control by said mode selecting means thereby to invert or not to invert said remaining part of said input address signal.

Claim 11

A semiconductor memory according to claim 7, wherein said first, second and third selecting means and said sequence control means are bidirectional.

Claim 12

A semiconductor memory according to claim 7, further comprising fourth selecting means connected to said first plurality control means and said mode selecting means for responding to the control of said mode selecting means to thereby supply a most significant address part and a least significant address part of said input address signal to a most significant address portion and a least significant address portion or vice versa, respectively, of said first decoder means, wherein a median significance address part is supplied to said second polarity control means.

Claim 13

A semiconductor memory according to claim 10, wherein said first, second and third selecting means and said sequence control means are bidirectional.