Patent US4933577A successfully refreshed from Google Patents.
US4933577A
Expired / Lapsed
US
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Output circuit for a programmable logic array
Assignee: Lattice Semiconductor Corp
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Filing: 1989-04-10
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Granted: 1990-06-12
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Expires: 2009-04-10
Abstract
Abstract An output circuit (50) is provided for a programmable logic array (PLA) integrated circuit. The output circuit (50) includes a flip flop (52) which stores a given output term from the array. The flip flop (52) contains a set input lead (S) and a reset input lead (R). The signals present at the set input, reset input, and clock leads are generated by programmable logic within the PLA. A multiplexer (54) is provided which receives the output data of the flip flop (52) and the signal constituting the input data for the flip flop. The multiplexer provides the data input signal on the multiplexer output lead (60) when both the set and reset input signals are true. However, if either or both the set and reset input signals are false, then the multiplexer (54) provides the Q output signal from the flip flop (52) on the multiplexer output lead (60). The multiplexer output signal is presented to a three-state buffer (62) which in turn drives an output pin.
Inventors
- 👤 Sing Y. Wong
- 👤 John M. Birkner
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 20:12
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17704; H03K19/17708; H03K19/17716
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
183 words
A PLA comprising: means for providing a plurality of input signals; means for providing a plurality of intermediate signals corresponding to the logical product of at least some of said input signals; means for providing a plurality of output signals corresponding to the logical sum of at least some of said intermediate signals; an output lead; flip flop means having a first input lead coupled to receive one of said output signals and a second input lead coupled to said output lead for storing said one output signal and providing said one stored output signal on said output lead or for receiving a signal from said second input lead and for storing said signal received from said second input lead, and wherein said flip flop means includes a preset control line, said flip flop means storing the signal on said second input lead in response to a preset signal on said preset control line, said flip flop means also including a clock line, said flip flop means for storing said one output signal in response to a clock signal on said clock line.
Claim 2
Dependent Claim
183 words
A PLA comprising: means for providing a plurality of input signals; means for providing a plurality of intermediate signals corresponding to the logical product of at least some of said input signals; means for providing a plurality of output signals corresponding to the logical sum of at least some of said intermediate signals; an output lead; flip flop means having a first input lead coupled to receive one of said output signals and a second input lead coupled to said output lead for storing said one output signal and providing said one stored output signal on said output lead or for receiving a signal from said second input lead and for storing said signal received from said second input lead, and wherein said flip flop means includes a preset control line, said flip flop means storing the signal on said second input lead in response to a preset signal on said preset control line, said flip flop means also including a clock line, said flip flop means for storing said one output signal in response to a clock signal on said clock line.
Claim 3
Dependent Claim
76 words
The PLA of claim 1 wherein in said flip flop means comprises a three state buffer for receiving the signal stored in said flip flop means and providing said signal stored in said flip flop means on said output lead, said three state buffer including a three state control input, said three state buffer going into a high impedance mode in response to a three state control signal being applied to said three state control input.
Claim 4
Dependent Claim
22 words
The PLA of claim 1 further comprising means for providing the signal on said output lead as one of said input signals.
Claim 5
Dependent Claim
93 words
A circuit comprising: a first input lead for receiving an input signal; an output lead; a second input lead for receiving a clock signal; storing means for receiving and storing said input signal in response to said clock signal on said second input lead; means coupled to said storing means and said output lead for providing the signal stored in said storing means on said output lead; a third input lead for receiving a control signal, said storing means storing a signal present at said output lead in response to said control signal.
Claim 6
Dependent Claim
93 words
A circuit comprising: a first input lead for receiving an input signal; an output lead; a second input lead for receiving a clock signal; storing means for receiving and storing said input signal in response to said clock signal on said second input lead; means coupled to said storing means and said output lead for providing the signal stored in said storing means on said output lead; a third input lead for receiving a control signal, said storing means storing a signal present at said output lead in response to said control signal.
Claim 7
Dependent Claim
63 words
The circuit of claim 4 wherein said means for providing comprises a three state buffer for receiving said stored input signal and providing said stored input signal on said output lead, said three state buffer having a three state control lead, said three state buffer going into a high impedance mode in response to a signal present on said three state control lead.
Claim 8
Dependent Claim
63 words
The circuit of claim 4 wherein said storing means is a flip flop having a clock lead and a preset control lead, said flip flop storing the signal at said first input lead in response to a signal on said clock lead, said flip flop storing the signal on said second input lead in response to the signal at said preset control lead.
Claim 9
Dependent Claim
37 words
The PLA of claim 1 wherein said circuit is constructed such that said flip flop means can store either said signal at said first input lead or the signal at said second input lead during normal operation.
Claim 10
Dependent Claim
26 words
Circuit of claim 4 wherein said circuit can store the signal at said first input lead or the signal at said output lead during normal operation.
References Cited (Backward Citations)
US4422072A
Cited
US4717912A
Cited
US4617479A
Cited
US4617479B1
Cited
US4609986A
Cited
US4684830A
Cited
EP0198677A2
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-06-11 | 1993-12-11 | 1994-06-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-06-11 | 1997-12-11 | 1998-06-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-06-11 | 2001-12-11 | 2002-06-12 | $7700.00 | Window Closed / Lapsed |