Patent US3150488A successfully refreshed from Google Patents.
EP0198677A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Programmable logic storage element for programmable logic devices
Assignee: Altera Corp
•
Filing: 1986-04-10
•
Granted: —
•
Expires: 2006-04-10
Abstract
Abstract 0 A storage element for use in a logic array including a flip-flop device (D-FF) and a complex logic circuit (18) interconnected in such a way that the output (29) of the complex logic circuit is an input to the flip-flop. A Toggle Flip-Flop Control (TFFC) signal, an invert control (INV) signal, and a clock (CLK) signal are also inputs to the complex logic circuit. The output of the flip-flop connects to an output pad (31), an internal direct feedback line (33) which is one of the means by which the flip-flop is connected to the complex logic circuit, and an external feedback bus (32) which leads back to an associated AND-OR array. The input to the complex logic circuit is generated by the standard AND-OR array which is programmable to some degree.
Inventors
- 👤 Kerry S. Veenstra
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-28 15:03
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/027; H03K3/037; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17704; H03K19/17708; H03K19/17716
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
237 words
Logic storage means for a programmable logi array which includes a programmable AND arra responsive to input data signals to develop pre determined product terms and an OR array respor sive to the said product terms and operative develop corresponding logic signals, the logic sto age means being for temporarily storing said logi signals and either outputing them to output term nals or returning them to said AND array an comprising: flip-flop means having first termin means for receiving a next state logic signal, set ond terminal means for receiving a clock signal, and output terminal means; and control logic means having a third terminal means coupled to said output terminal means for receiving a feedback signal, fourth terminal means for receiving an invert control signal, fifth terminal means for receiving a toggle control signal, sixth terminal means connected to said first terminal means, and input terminal means for receiving logic signals from said OR array, said control logic circuit means being responsive to said feedback signal, said invert control signal and said toggle control signal, and operative to develop on said sixth terminal means a signal having a predetermined relationship to the logic signal input on said input terminal means, whereby said flip-flop means and said control logic circuit means may be selectively caused to emulate particular types of flip-flop means determined at least in part by said invert control signal and said toggle control signal.
Claim 2
Dependent Claim
237 words
Logic storage means for a programmable logi array which includes a programmable AND arra responsive to input data signals to develop pre determined product terms and an OR array respor sive to the said product terms and operative develop corresponding logic signals, the logic sto age means being for temporarily storing said logi signals and either outputing them to output term nals or returning them to said AND array an comprising: flip-flop means having first termin means for receiving a next state logic signal, set ond terminal means for receiving a clock signal, and output terminal means; and control logic means having a third terminal means coupled to said output terminal means for receiving a feedback signal, fourth terminal means for receiving an invert control signal, fifth terminal means for receiving a toggle control signal, sixth terminal means connected to said first terminal means, and input terminal means for receiving logic signals from said OR array, said control logic circuit means being responsive to said feedback signal, said invert control signal and said toggle control signal, and operative to develop on said sixth terminal means a signal having a predetermined relationship to the logic signal input on said input terminal means, whereby said flip-flop means and said control logic circuit means may be selectively caused to emulate particular types of flip-flop means determined at least in part by said invert control signal and said toggle control signal.
Claim 3
Dependent Claim
116 words
Logic storage means according to claim 1, wherein said flip-flop means is a D-type flip-flop and wherein said control logic circuit means includes a first exclusive-OR gate having one input connected to said fourth terminal means and other input connected to said input terminal means, a second exclusive-OR gate having one input coupled to the output of said first exclusive OR gate and another input coupled to said third terminal means, and a multiplexer having a first input coupled to said fifth terminal means, a second input coupled to the output of said first exclusive-OR gate, a third input coupled to the output of said second exclusive-OR gate and an output forming said sixth terminal means.
Claim 4
Dependent Claim
99 words
Logic storage means according to. claim 1, wherein said flip-flop means is a D-type flip-flop and wherein said control logic circuit means includes a NAND gate having one input coupled to said third terminal means and another input coupled to said fifth terminal means, an exclusive-NOR gate having one input coupled to the output of said NAND gate and another input coupled to said fourth terminal means, and an exclusive-OR gate having one input coupled to the output of said exclusive-NOR gate and another input coupled to said input terminal means, the output thereof forming said sixth terminal means.
Claim 5
Dependent Claim
15 words
Logic storage means according to claim 1, wherein said flip-flop means is a T-type flip-flop.
Claim 6
Dependent Claim
36 words
Logic storage means according to claim 1, wherein the components of said control logic circuit means are selected and interconnected in such manner as to satisfy the requirements of the "next state diagram" of Table 1.
Claim 7
Dependent Claim
49 words
A programmable logic array comprising programmable AND array means which responds to input data signals and developed predetermined product terms; OR array means responsive to the said product terms and operative to develop corresponding logic signals; and logic storage means according to any one of claims 1 to 5.
Claim 8
Dependent Claim
75 words
A programmable logic array according to claim 6, wherein said AND array includes a plurality of input circuit means for receiving input signals and at least one of said input circuit means is coupled to said output terminal means, and wherein said AND array is programmed to function in accordance with a selected set of the parameters set forth in Table 2 whereby said logic array functions to emulate the- selected particular type of flip-flop.
Claim 9
Dependent Claim
80 words
A programmable logic array according to claim 6, when appendant to claim 2, wherein said AND array includes a plurality of input circuit means for receiving input signals and at least one of said input circuit means is coupled to said output terminal means, and wherein said AND array is programmed to function in accordance with a selected set of the parameters set forth in Table 2 whereby said logic array functions to emulate the selected particular type of flip-flop.
Claim 10
Dependent Claim
80 words
A programmable logic array according to claim 6 when appendant to claim 3, wherein said AND array includes a plurality of input circuit means for receiving input signals and at least one of said input circuit means is coupled to said output terminal means, and wherein said AND array is programmed to function in accordance with a selected set of the parameters set forth in Table 2 whereby said logic array functions to emulate the selected particular type of flip-flop.
Claim 11
Dependent Claim
79 words
A programmable logic array according to claim 6, when appendant to claim·5, wherein said AND array includes a plurality of input circuit means for receiving input signals and at least one of said input circuit means is coupled to said output terminal means, and wherein said AND array is programmed to function in accordance with a selected set of the parameters set forth in Table 2 whereby said logic array functions to emulate the selected particular type of flip-flop.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.