US4931972A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Multiple-input digital filter
Assignee: Toshiba Corp
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Filing: 1988-05-24
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Granted: 1990-06-05
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Expires: 2008-05-24
Abstract
Abstract A multiple-input digital filter capable of filtering a plurality of digital input signals with a single filtering device first latches the input signals and then sequentially selects each of the digital input signals for output to a counter circuit. The counter circuit, which is preset by the previous count value for the corresponding digital input signal, counts up or down depending on the digital input signal. When the count value reaches its maximum, a decision value signal is set for the corresponding digital input signal until the count value for that digital input signal returns to the minimum value. The count values are stored in a shift register which supplies the count value corresponding to the digital input signal as a preset value to the counter. A second shift register stores the decision values corresponding to each of the digital input signals which are then latched for simultaneous output.
Inventors
- 👤 Yoshimori Obata
- 👤 Makoto Toko
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 06:43
CPC Classifications
H; H03; H03H; H03H7/00; H03H17/00; H03H17/02; H03H17/0283; H03H17/0292; H03H2218/00; H03H2218/06
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
180 words
A multiple-input digital filter comprising: receiver means for receiving a plurality of digital input signals at one time and outputting one of the digital signals at a time; counter means, coupled to the receiving means, for conducting predetermined counting operations according to the outputted values of the digital input signals, the counting operations producing count values each corresponding to one of the digital input signals; decision circuit means, coupled to the counter means, for outputting a predetermined decision value signal from a time when each count value corresponding to one of the digital input signals reaches a first predetermined value to a time when the same count value reaches a second predetermined value; holding means, coupled to the counter means, for holding the count values and for supplying one of the count values as a preset value to the counter means for a corresponding digital input signal; and output circuit means, coupled to the decision circuit means, for latching each of the decision values corresponding to the digital input signals and for simultaneously outputting a plurality of the decision values.
Claim 2
Dependent Claim
180 words
A multiple-input digital filter comprising: receiver means for receiving a plurality of digital input signals at one time and outputting one of the digital signals at a time; counter means, coupled to the receiving means, for conducting predetermined counting operations according to the outputted values of the digital input signals, the counting operations producing count values each corresponding to one of the digital input signals; decision circuit means, coupled to the counter means, for outputting a predetermined decision value signal from a time when each count value corresponding to one of the digital input signals reaches a first predetermined value to a time when the same count value reaches a second predetermined value; holding means, coupled to the counter means, for holding the count values and for supplying one of the count values as a preset value to the counter means for a corresponding digital input signal; and output circuit means, coupled to the decision circuit means, for latching each of the decision values corresponding to the digital input signals and for simultaneously outputting a plurality of the decision values.
Claim 3
Dependent Claim
53 words
The filter according to claim 1, wherein the receiver means includes: latch circuit means for receiving and latching the plurality of digital input signals at one time and for supplying latched values of the digital input signals, and selector means, coupled to the latch circuit means, for outputting one of the latched values.
Claim 4
Dependent Claim
20 words
The filter according to claim 2, wherein the selector means comprises means for sequentially outputting one of the latched values.
Claim 5
Dependent Claim
14 words
The filter according to claim 1, wherein the holding means comprises a shift register.
Claim 6
Dependent Claim
40 words
The filter according to claim 1, further comprising: second holding means, coupled to the decision circuit means, for holding the decision values and for supplying one of the decision values for a corresponding count value to the decision circuit means.
Claim 7
Dependent Claim
29 words
The filter according to claim 5, wherein the output circuit means includes latch circuit means, coupled to the second holding means, for simultaneously outputting the plurality of decision values.
Claim 8
Dependent Claim
15 words
The filter according to claim 5, wherein the second holding means comprises a shift register.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-06-04 | 1993-12-04 | 1994-06-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-06-04 | 1997-12-04 | 1998-06-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-06-04 | 2001-12-04 | 2002-06-05 | $7700.00 | Window Closed / Lapsed |