US4081130A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Filter-type pulse detection means
Assignee: InterDigital Technology Corp
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Filing: 1976-08-17
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Granted: 1978-03-28
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Expires: 1996-08-17
Abstract
Abstract A filter-type pulse counter system which separates pulses of desired frequencies from pulses of undesired frequencies, filters out the pulses of undesired frequencies, and then accepts and counts only those pulses of the desired frequencies.
Inventors
- 👤 Duane Ridgely Bolgiano
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 22:51
CPC Classifications
H; H04; H04M; H04M19/00; H04M19/02; H04M19/04; H03; H03K; H03K21/00; H03K21/02; H03K21/026
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
162 words
A filter-type pulse counter system which separates pulses of a predetermined frequency from other pulses transmitted from a source of said pulses, filters out said other pulses, and then accepts and counts those pulses of said predetermined frequency which occur during a predetermined time interval, said counter system comprising first and second pulse counters arranged in cascade to receive signal pulses from a source thereof, a source of clock pulses connected to said cascaded pulse counters to apply clock pulses thereto, said cascaded pulse counters being enabled by said signal pulses to count said clock pulses, an acceptance gate connected to and controlled by said cascaded counters and to said source of signal pulses, said acceptance gate being adapted to accept only those signal pulses where the duration between the start of each successive pulse lies beteeen predetermined limits as determined by the cascaded counter, and a third counter connected to said acceptance gate to receive and count the accepted signal pulses.
Claim 2
Dependent Claim
162 words
A filter-type pulse counter system which separates pulses of a predetermined frequency from other pulses transmitted from a source of said pulses, filters out said other pulses, and then accepts and counts those pulses of said predetermined frequency which occur during a predetermined time interval, said counter system comprising first and second pulse counters arranged in cascade to receive signal pulses from a source thereof, a source of clock pulses connected to said cascaded pulse counters to apply clock pulses thereto, said cascaded pulse counters being enabled by said signal pulses to count said clock pulses, an acceptance gate connected to and controlled by said cascaded counters and to said source of signal pulses, said acceptance gate being adapted to accept only those signal pulses where the duration between the start of each successive pulse lies beteeen predetermined limits as determined by the cascaded counter, and a third counter connected to said acceptance gate to receive and count the accepted signal pulses.
Claim 3
Dependent Claim
53 words
The system of claim 1 wherein a fourth counter is connected to said acceptance gate and wherein each accepted signal pulse resets the fourth counter until the last of a series of accepted pulses is reached, at which time said fourth counter is not reset by any succeeding pulses and counts to conclusion.
Claim 4
Dependent Claim
83 words
The system of claim 1, wherein a fourth counter is connected to said acceptance gate, said fourth counter being reset by each accepted signal pulse, said fourth counter also being connected to said source of lock pulses to count said clock pulses, and a second gate connected between said acceptance gate and said third counter, said second gate being actuated by said fourth counter to terminate the counting of said third counter when said fourth counter reaches a predetermined count of clock pulses.
Claim 5
Dependent Claim
40 words
The system of claim 3 wherein additional gates which are connected to both said third and fourth counters are adapted to pass the count stored in said third counter to a sink when said fourth counter reaches said predetermined count.
Claim 6
Dependent Claim
22 words
The system of claim 4 wherein the count that is stored in said third counter is passed to said sink bit serially.
Claim 7
Dependent Claim
27 words
The system of claim 1 wherein the first of said signal pulses is filtered out by said first and second counters to avoid detection of random noise.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-03-27 | 1981-09-26 | 1982-03-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-03-27 | 1985-09-26 | 1986-03-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-03-27 | 1989-09-26 | 1990-03-28 | $7700.00 | Window Closed / Lapsed |