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Patent US4930106A successfully refreshed from Google Patents.
US4930106A
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Dual cache RAM for rapid invalidation
Assignee: Unisys Corp
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Filing: 1988-08-29
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Granted: 1990-05-29
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Expires: 2008-08-29
Abstract
Abstract A cache buffer for a multiprocessor system utilizes two RAMs to store validity bits. Use of these RAMs greatly reduces chip area required to implement the validity buffer and reduces interconnection foil (printed connectors) and hence propagation time. An initial clear state is written into all of the memory locations of both RAMs. One of the RAMs then becomes the active validity bit RAM and the other a standby. When a fast invalidate command is received, upon an invalidate parity error indication from a memory readout, for example, the standby RAM is switched to the active RAM, and the validity bits of the formerly active RAM are cleared in sequential write cycles after it is switched to a standby state.
Inventors
- 👤 Michael Danilenko
- 👤 Clarence W. DeKarske
- 👤 John E. Larson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 16:46
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/12
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
180 words
Storage means for storing validity bits in a multiprocessor cache memory comprising a plurality of random access storage means, switch means for initially enabling a first one of said plurality of random access storage means thereby enabling it to function as an active store of said validity bits in an operating cache memory, and for disabling the others of said plurality of random access storage means from functioning as an active store of said validity bits for said operating cache memory, said switch means also being operable to disable said first one of said random access storage means and to enable one other of said plurality of said random access storage means for function as an active store of said validity bits upon receipt of an invalidate signal by said cache memory means, and write means for writing into memory locations of said first one of said random access storage means following the disablement of said first one of said random access storage means by said switch means until all of said memory locations are at a common logic level.
Claim 2
Dependent Claim
180 words
Storage means for storing validity bits in a multiprocessor cache memory comprising a plurality of random access storage means, switch means for initially enabling a first one of said plurality of random access storage means thereby enabling it to function as an active store of said validity bits in an operating cache memory, and for disabling the others of said plurality of random access storage means from functioning as an active store of said validity bits for said operating cache memory, said switch means also being operable to disable said first one of said random access storage means and to enable one other of said plurality of said random access storage means for function as an active store of said validity bits upon receipt of an invalidate signal by said cache memory means, and write means for writing into memory locations of said first one of said random access storage means following the disablement of said first one of said random access storage means by said switch means until all of said memory locations are at a common logic level.
Claim 3
Dependent Claim
36 words
A validity bit storage means as claimed in claim 1 comprising clear means for initially writing a common logic level into all of the memory locations of all of said plurality of random access storage means.
References Cited (Backward Citations)
US3845474A
Cited
US4825412A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-05-28 | 1993-11-27 | 1994-05-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-05-28 | 1997-11-27 | 1998-05-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-05-28 | 2001-11-27 | 2002-05-29 | $7700.00 | Window Closed / Lapsed |