US4929947A
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Constant width pulse distribution in a digital to analog converter for serial digital data
Assignee: Nippon Precision Circuits Inc
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Filing: 1988-04-04
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Granted: 1990-05-29
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Expires: 2008-04-04
Abstract
Abstract A digital-to-analog converter comprising: a distributing circuit (2, 3, 4, 5; 2, 13, 14-26) for distributing data pulses, which are bit-serially supplied at constant time intervals, into a plurality of routes and for providing them as pulses having a constant width; and a converting circuit (12) for adding together the pulses from the distributing circuit and thereby for converting them to an analog output. Such a circuit arrangement can provide pulses for conversion to analog form which all have an identical waveform and an identical area, and errors caused by the difference between the rise and fall times of the pulses can be eliminated and therefore D/A conversion characteristics can be improved.
Inventors
- 👤 Akira Toyama
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 22:07
CPC Classifications
H; H03; H03M; H03M3/00; H03M3/30; H03M3/322; H03M3/368; H03M3/37; H03M3/372; H03M3/50
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
106 words
A digital to analog converting circuit for converting serial digital data into analog signal output, comprising: distributing means receptive of serial bit data pulses supplied sequentially for distributing the data pulses to at least two parallel channels, each distributed pulse of each channel having a constant width and a constant time interval between a termination of one pulse and a beginning of the next pulse in each channel; converting means disposed in each channel for converting each pulse having said constant width into an analog value; and adding means for adding the analog values of said each channel and producing an analog signal output corresponding thereto.
Claim 2
Dependent Claim
106 words
A digital to analog converting circuit for converting serial digital data into analog signal output, comprising: distributing means receptive of serial bit data pulses supplied sequentially for distributing the data pulses to at least two parallel channels, each distributed pulse of each channel having a constant width and a constant time interval between a termination of one pulse and a beginning of the next pulse in each channel; converting means disposed in each channel for converting each pulse having said constant width into an analog value; and adding means for adding the analog values of said each channel and producing an analog signal output corresponding thereto.
Claim 3
Dependent Claim
173 words
A digital to analog converter comprising: first means receptive of serial data pulses at constant time intervals for distributing the pulses to at least two parallel channels; second means disposed in each channel for converting the distributed pulses to pulses of constant width; third means for adding the pulses of constant width together in an analog form; wherein for two channels the first means comprises a first AND gate receptive of the serial data pulses and a clock signal synchronized thereto and having an output, and a first flip-flop receptive of the output of the AND gate at a clock input and having Q and Q outputs, and two second AND gates receptive of the Q and Q outputs respectively for gating same with the original data pulses and having outputs; and wherein the second means comprises two second D-type flip-flops receptive of the outputs of the second AND gates at D inputs thereof and of the clock signal at the clock inputs thereof for generating the constant width pulses at outputs thereof.
Claim 4
Dependent Claim
173 words
A digital to analog converter comprising: first means receptive of serial data pulses at constant time intervals for distributing the pulses to at least two parallel channels; second means disposed in each channel for converting the distributed pulses to pulses of constant width; third means for adding the pulses of constant width together in an analog form; wherein for two channels the first means comprises a first AND gate receptive of the serial data pulses and a clock signal synchronized thereto and having an output, and a first flip-flop receptive of the output of the AND gate at a clock input and having Q and Q outputs, and two second AND gates receptive of the Q and Q outputs respectively for gating same with the original data pulses and having outputs; and wherein the second means comprises two second D-type flip-flops receptive of the outputs of the second AND gates at D inputs thereof and of the clock signal at the clock inputs thereof for generating the constant width pulses at outputs thereof.
Claim 5
Dependent Claim
251 words
A digital to analog converter comprising: first means receptive of serial data pulses at constant time intervals for distributing the pulses to at least two parallel channels; second means disposed in each channel for converting the distributed pulses to pulses of constant width; third means for adding the pulses of constant width together in an analog form; wherein for a plurality of channels the first means comprises a first AND gate receptive of the serial data pulses and a clock signal synchronized thereto and having an output and a ring counter receptive of the AND gate output at a clock input thereof and having a plurality of outputs; wherein the second means comprises a plurality of D-type flip-flops each having a clock input connected to an output of the ring counter, a reset input and an output, a plurality of shift registers each having a shift input connected to an output of the D-type flip-flops, a clock input receptive of the clock signal and an output, and a plurality of second AND gates each having an input connected to the output of one D-type flip-flop and the output of one shift register associated with the one D-type flip-flop and having an output connected to the reset input of the one D-type flip-flop; and wherein the third means comprises a latch circuit having a plurality of inputs receptive of the outputs of the D-type flip-flops and having a plurality of outputs, and means for adding the plurality of outputs in analog form.
Claim 6
Dependent Claim
251 words
A digital to analog converter comprising: first means receptive of serial data pulses at constant time intervals for distributing the pulses to at least two parallel channels; second means disposed in each channel for converting the distributed pulses to pulses of constant width; third means for adding the pulses of constant width together in an analog form; wherein for a plurality of channels the first means comprises a first AND gate receptive of the serial data pulses and a clock signal synchronized thereto and having an output and a ring counter receptive of the AND gate output at a clock input thereof and having a plurality of outputs; wherein the second means comprises a plurality of D-type flip-flops each having a clock input connected to an output of the ring counter, a reset input and an output, a plurality of shift registers each having a shift input connected to an output of the D-type flip-flops, a clock input receptive of the clock signal and an output, and a plurality of second AND gates each having an input connected to the output of one D-type flip-flop and the output of one shift register associated with the one D-type flip-flop and having an output connected to the reset input of the one D-type flip-flop; and wherein the third means comprises a latch circuit having a plurality of inputs receptive of the outputs of the D-type flip-flops and having a plurality of outputs, and means for adding the plurality of outputs in analog form.
Claim 7
Dependent Claim
17 words
The digital to analog converter according to claim 3, wherein the plurality of channels comprises four channels.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-05-28 | 1993-11-27 | 1994-05-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-05-28 | 1997-11-27 | 1998-05-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-05-28 | 2001-11-27 | 2002-05-29 | $7700.00 | Window Closed / Lapsed |