Digital-to-analog converter utilizing pulse duration modulation

Claim 2

In a digital-to-analog converter, the combination of a device having a plurality of output leads with signals thereon representing bits in a binary number, a source of pulses, a binary counter connected to said source of pulses, said binary counter comprising a plurality of bistable units connected in cascade, each bistable unit having a first output terminal connected to the input of the next successive bistable unit in the counter and a second output terminal, the signals appearing on said second terminals being the compliments of those on the first terminals, the number of bistable units in said counter being equal to the number of output leads of said device, first AND logic circuit devices connected to selected ones of the output terminals of said counter bistable units, second AND logic circuit devices connected to said device output leads, said second logic circuit devices also being connected to said first logic circuit devices and at least one of said bistable unit output terminals, and means for filtering the combined outputs of said second logic circuit devices to derive an analog signal.

Claim 3

In a digital-to-analog converter, the combination of a device having a plurality of output leads with signals thereon representing bits in a binary number, a source of pulses, a binary counter connected to said source of pulses, said binary counter comprising a plurality of bistable units connected in cascade, each bistable unit having a first output terminal connected to the input of the next successive bistable unit in the counter and a second output terminal, the signals appearing on said second terminals being the compliments of those on the first terminals, the number of bistable units in said counter being equal to the number of output leads of said device, first logic circuit means connected to selected ones of the output terminals of said counter bistable units, second logic circuit means connected to said device output leads, said first logic circuit means comprising a first plurality of logic circuits equal in number to one less than the number of bistable units in said counter and said second logic circuit means comprising a second plurality of logic circuits equal in number to the number of said device output leads, means connecting selected ones of said output terminals of the counter bistable units to the inputs of said first plurality of logic circuits, means connecting one of the output terminals of one of said counter bistable units and one of said deVice output leads to the inputs of one of said logic circuits in said second plurality of logic circuits, means connecting each of the remaining device output leads to the input of an associated one of the remaining logic circuits in said second plurality of logic circuits along with the output of a selected one of said logic circuits in said first plurality of logic circuits, and a further logic circuit connected to the outputs of all of said logic circuits in said second plurality of logic circuits.

Claim 4

In a digital-to-analog converter, the combination of a device having a plurality of output leads with signals thereon representing bits in a binary number, a source of pulses, a binary counter connected to said source of pulses, said binary counter comprising a plurality of bistable units connected in cascade, each bistable unit having a first output terminal connected to the input of the next successive bistable unit in the counter and a second output terminal, the signals appearing on said second terminals being the compliments of those on the first terminals, the number of bistable units in said counter being equal to the number of output leads of said device, first logic circuit means connected to selected ones of the output terminals of said counter bistable units, second logic circuit means connected to said device output leads, said first logic circuit means comprising a first plurality of logic circuits equal in number to one less than the number of bistable units in said counter and said second logic circuit means comprising a second plurality of logic circuits equal in number to the number of said device output leads, means connecting selected ones of said output terminals of the counter bistable units to the inputs of said first plurality of logic circuits, means connecting one of the output terminals of one of said counter bistable units and one of said deVice output leads to the inputs of one of said logic circuits in said second plurality of logic circuits, means connecting each of the remaining device output leads to the input of an associated one of the remaining logic circuits in said second plurality of logic circuits along with the output of a selected one of said logic circuits in said first plurality of logic circuits, and a further logic circuit connected to the outputs of all of said logic circuits in said second plurality of logic circuits.

Claim 5

The digital-to-analog converter of claim 2 wherein the logic circuits in both said first and second pluralities of logic circuits comprise AND circuits.

Claim 6

The digital-to-analog converter of claim 3 wherein the AND logic circuits in said first plurality of logic circuits are connected at their inputs to the second output terminals of all but the last of said bistable units in said binary counter, and are also connected at their inputs to the first output terminals of all but the first of said bistable units in said binary counter.

Claim 7

The digital-to-analog converter of claim 4 wherein one of said AND logic circuits in said first plurality of logic circuits is connected to all of said bistable units in said binary counter, and the remaining of said AND logic circuits in said first plurality are successively connected to one less of the bistable units until the last logic circuit in said first plurality is connected to only two of the bistable units in said binary counter.

Claim 8

The digital-to-analog converter of claim 5 wherein said one AND logic circuit in said first plurality of logic circuits is connected at its output to the input of the AND circuit in said second plurality of logic circuits to which the output lead of said device is connected representing the least significant bit in said binary number, and said last AND logic circuit in said first plurality of logic circuits is connected through its output lead to the input of the AND circuit in said second plurality of logic circuits to which the output lead of said device is connected representing the next to the most significant bit in said binary number.