Serial digital-to-analog converter

Claim 2

A digital-to-analog converter comprising: first and second shift registers each having a data input terminal for receiving binary digits that are synchronized with a clock pulse train, a data output terminal and a clock terminal, such that on application of a clock pulse to the clock terminal a binary digit present at the data input terminal is made available at the output terminal, the data input terminals of the first and second shift registers being connected together; means for applying clock pulses alternately to the clock terminals of the first and second shift registers, whereby each shift register receives clock pulses at substantially half the repetition rate of the clock pulse train; first and second current switches associated with the first and second shift registers respectively, each switch having a current input terminal and two current output terminals and being operative to steer current supplied to its current input terminal to one of its two current output terminals if the binary digit at the output of the associated shift register has one of two possible values and to steer current to the other of its two current output terminals if the binary digit has the other of the two possible values; first and second current sources for supplying equal, constant currents and connected to the current input terminals of the first and second current switches respectively; a third current switch having a current input terminal and two current output terminals, the current output terminals being connected to the current input terminals of the first and second switches respectively and the third switch being operative to steer current supplied to its current input terminal to its two current output terminals in alternating fashion in response to successive clock pulses applied to the first shift register, and a third current source for supplying a constant current and connected to the current input terminal of the third current switch.

Claim 3

A digital-to-analog converter according to claim 1, wherein each shift register comprises at least one D flip-flop.

Claim 4

A digital-to-analog converter according to claim 1, wherein each shift register has two complementary data output terminals and each current switch comprises a differential amplifier having two data input terminals connected to the complementary data output terminals respectively of the associated shift register.

Claim 5

A digital-to-analog converter according to claim 3, comprising a divide-by-two circuit for receiving an input clock signal having a reception rate equal to the rate at which data is applied to the shift registers and for providing two complementary clock signals having half the repetition rate of the input clock signal, and wherein the third current switch comprises a differential amplifier having two control terminals connected for receiving the two complementary clock signals respectively.

Claim 6

A digital-to-analog converter (DAC) comprising: first and second serial in, parallel out shift registers each having N stages, where N is a positive integer, each shift register having a data input terminal for receiving binary digits at a predetermined data rate, first through Nth output terminals and a clock terminal, such that on application of a clock pulse to the clock terminal the binary digit present at the input terminal is made available at the first output terminal and the binary digits present at the first through (N-1)th output terminals are made available at the second through Nth output terminals, the data input terminals of the two shift registers being connected together; means for applying clock pulses to the clock terminals of each of the first and second shift registers at a rate equal to substantially half of the data rate at which binary digits are applied to the data input terminals and in alternating fashion; first and second current switch arrays associated with the first and second shift registers respectively, each switch array comprising N switches associated respectively with the N stages of the associated shift register and each switch having a current input terminal and two current output terminals and being operative to steer current supplied to its current input terminal to one of its two current output terminals if the binary digit at the associated output terminal of the associated shift register has one of two values and to steer current to the other of its two current output terminals if the binary digit at the associated output terminal has the other of the two values; 2 N current sources supplying equal, constant currents and connected to the current input terminals of the current switches respectively; a third array of current switches comprising N switches each having a current input terminal and two current output terminals, the ith (where i is an integer from 1 to N) switch of the third array having its current output terminals connected to the input terminals of the ith switches of the first and second arrays respectively and being operative to steer current supplied to its input terminal to its two output terminals in alternating fashion in response to consecutive clock pulses; and N additional current sources supplying currents and connected respectively to the current input terminals of the N switches of the third array.

Claim 7

A digital-to-analog converter (DAC) comprising: first and second serial in, parallel out shift registers each having N stages, where N is a positive integer, each shift register having a data input terminal for receiving binary digits at a predetermined data rate, first through Nth output terminals and a clock terminal, such that on application of a clock pulse to the clock terminal the binary digit present at the input terminal is made available at the first output terminal and the binary digits present at the first through (N-1)th output terminals are made available at the second through Nth output terminals, the data input terminals of the two shift registers being connected together; means for applying clock pulses to the clock terminals of each of the first and second shift registers at a rate equal to substantially half of the data rate at which binary digits are applied to the data input terminals and in alternating fashion; first and second current switch arrays associated with the first and second shift registers respectively, each switch array comprising N switches associated respectively with the N stages of the associated shift register and each switch having a current input terminal and two current output terminals and being operative to steer current supplied to its current input terminal to one of its two current output terminals if the binary digit at the associated output terminal of the associated shift register has one of two values and to steer current to the other of its two current output terminals if the binary digit at the associated output terminal has the other of the two values; 2 N current sources supplying equal, constant currents and connected to the current input terminals of the current switches respectively; a third array of current switches comprising N switches each having a current input terminal and two current output terminals, the ith (where i is an integer from 1 to N) switch of the third array having its current output terminals connected to the input terminals of the ith switches of the first and second arrays respectively and being operative to steer current supplied to its input terminal to its two output terminals in alternating fashion in response to consecutive clock pulses; and N additional current sources supplying currents and connected respectively to the current input terminals of the N switches of the third array.

Claim 8

A digital-to-analog converter comprising: P shift registers, where P is a positive integer greater than 1, each shift register having a data input terminal for receiving binary digits at a predetermined data rate, first through Nth output terminals, where N is a positive integer, and a clock terminal, such that on application of a clock pulse to the clock terminal the binary digit present at the data input terminal is made available at the first output terminal and the binary digits present at the first through (N-1)th output terminals are made available at the second through Nth output terminals respectively, the data input terminals of the P shift registers being connected together; means for applying clock pulses sequentially to the clock terminals of the P shift registers, whereby each shift register receives clock pulses at substantially one-pth of the predetermined data rate; P current switch arrays associated with the P shift registers respectively, each switch array comprising N switches associated respectively with the N output terminals of the associated shift register and each switch having a current input terminal and two current output terminals and being operative to steer current supplied to its current input terminal to one of its two current output terminals if the binary digit at the associated output terminal has one of two values and to steer current to the other of its two current output terminals if the binary digit has the other of the two possible values; N×P current sources for supplying equal, constant currents and connected to the current input terminals of the current switches respectively; an array of N additional current switches each having a current input terminal and P current output terminals, the ith (where i is an integer from 1 to N) switch of the array of additional current switches having its P current output terminals connected respectively to the current input terminals of the ith current switches of the P current switch arrays and each additional switch being operative to steer current supplied to its current input terminal to its P current output terminals sequentially; and N additional current sources for supplying constant currents and connected to the current input terminals of the N additional current switches respectively.

Claim 9

A digital-to-analog converter comprising: P shift registers, where P is a positive integer greater than 1, each shift register having a data input terminal for receiving binary digits at a predetermined data rate, first through Nth output terminals, where N is a positive integer, and a clock terminal, such that on application of a clock pulse to the clock terminal the binary digit present at the data input terminal is made available at the first output terminal and the binary digits present at the first through (N-1)th output terminals are made available at the second through Nth output terminals respectively, the data input terminals of the P shift registers being connected together; means for applying clock pulses sequentially to the clock terminals of the P shift registers, whereby each shift register receives clock pulses at substantially one-pth of the predetermined data rate; P current switch arrays associated with the P shift registers respectively, each switch array comprising N switches associated respectively with the N output terminals of the associated shift register and each switch having a current input terminal and two current output terminals and being operative to steer current supplied to its current input terminal to one of its two current output terminals if the binary digit at the associated output terminal has one of two values and to steer current to the other of its two current output terminals if the binary digit has the other of the two possible values; N×P current sources for supplying equal, constant currents and connected to the current input terminals of the current switches respectively; an array of N additional current switches each having a current input terminal and P current output terminals, the ith (where i is an integer from 1 to N) switch of the array of additional current switches having its P current output terminals connected respectively to the current input terminals of the ith current switches of the P current switch arrays and each additional switch being operative to steer current supplied to its current input terminal to its P current output terminals sequentially; and N additional current sources for supplying constant currents and connected to the current input terminals of the N additional current switches respectively.