Patent US4929916A successfully refreshed from Google Patents.
US4929916A
Expired / Lapsed
US
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Circuit for detecting a lock of a phase locked loop
Assignee: NEC Electronics Corp
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Filing: 1989-03-10
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Granted: 1990-05-29
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Expires: 2009-03-10
Abstract
Abstract A circuit for detecting a lock of a phase locked loop comprising a phase comparator receiving a first signal and a second signal for generating a phase difference signal, a waveform shaping circuit connected to receive the phase difference signal for generating an output signal when the phase difference signal indicates a phase difference exceeding a predetermined value, and a multi-stage counter having a frequency division function and having a reset input connected to receive the output signal of the waveform shaping circuit. An input control circuit is connected to receive the first signal and an output of the multi-stage counter and has an output connected to an input of the multi-stage counter for allowing the first signal to be applied to the multi-stage counter only when the output of the multi-stage counter is at a predetermined logic level. The output of the counter provides an lock output.
Inventors
- 👤 Shinri Fukuda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 18:17
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/085; H03L7/095; Y; Y10; Y10S; Y10S331/00; Y10S331/02
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
144 words
A circuit for detecting a lock of a phase locked loop comprising phase comparison means receiving a first signal and a second signal for generating a phase difference signal, waveform shaping means connected to receive the phase difference signal for generating an output signal when the phase difference signal indicates a phase difference exceeding a predetermined value, a multi-stage counter having a frequency division function and having a reset input connected to receive the output signal of the waveform shaping means, input control means connected to receive the first signal and an output of the multi-stage counter and having an output connected to an input of the multi-stage counter for allowing the first signal to be applied to the multi-stage counter only when the output of the multi-stage counter is at a predetermined logic level, the output of the counter providing an lock output.
Claim 2
Dependent Claim
144 words
A circuit for detecting a lock of a phase locked loop comprising phase comparison means receiving a first signal and a second signal for generating a phase difference signal, waveform shaping means connected to receive the phase difference signal for generating an output signal when the phase difference signal indicates a phase difference exceeding a predetermined value, a multi-stage counter having a frequency division function and having a reset input connected to receive the output signal of the waveform shaping means, input control means connected to receive the first signal and an output of the multi-stage counter and having an output connected to an input of the multi-stage counter for allowing the first signal to be applied to the multi-stage counter only when the output of the multi-stage counter is at a predetermined logic level, the output of the counter providing an lock output.
Claim 3
Dependent Claim
46 words
A circuit claimed in claim 1 wherein the waveform shaping means includes an integrater having an input connected to receive the phase difference signal and a schmitt circuit connected to an output of the integrater and an output connected to the reset input of the counter.
Claim 4
Dependent Claim
59 words
A circuit claimed in claim 2 wherein the integrater is composed of an analog integrater including a resister having its one end connected to receive the phase difference signal and a capacitor connected at its one end to the other end of the resister and an input of the schmitt circuit, the other end of the capacitor being grounded.
Claim 5
Dependent Claim
94 words
A circuit claimed in claim 1 wherein the multi-stage counter is an N-stage counter (N is an integer not less than 2) having a final stage which generates a low level output signal when 2 N-1 pulses are counted by the N-stage counter, and wherein the input control means includes an AND gate having a first input connected to receive the first signal and a second input connected to an output of the N-stage counter, an output and the AND gate being connected to an input of a first stage of the N-stage counter.
References Cited (Backward Citations)
US4122405A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-05-28 | 1993-11-27 | 1994-05-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-05-28 | 1997-11-27 | 1998-05-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-05-28 | 2001-11-27 | 2002-05-29 | $7700.00 | Window Closed / Lapsed |