US4926427A
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Software error detection apparatus
Assignee: Siemens AG
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Filing: 1989-04-03
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Granted: 1990-05-15
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Expires: 2009-04-03
Abstract
Abstract A software error detection circuit is described which supplements the known concept of a simple watch dog timer. The same clock pulse used to clock and time out a watch dog timer implements the addressing of a program memory. A comparison is then made of output data with data on a data bus. A failed comparison then raises an alarm faster and more efficiently than a timer circuit alone. Furthermore, in a parallel data bus environment a predetermined data check of adjacent bus line data is recommended over an all data or a random data check.
Inventors
- 👤 Duane Remein
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 15:25
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/0703; G06F11/0751; G06F11/0763; G06F11/0754; G06F11/0757; G06F11/36; G06F11/362; G06F11/3648
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
133 words
A circuit for the detection of software errors comprising: a timer circuit clocked by a clock pulse for providing an output when a predetermined period of time lapses; a control circuit for providing a sequence of data output values responsive to the clock pulse, comprising a counter responsive to said clock pulse, and a multiplexer; a comparator for comparing each one of said sequence of data output values from the control circuit with a data bus and for generating an output signal when the one of the data output values from the control circuit does not equal the corresponding one of the data input values from the data bus; and a decision circuit for generating an alarm signal when either the predetermined period of time lapses or the comparaator generates the output signal.
Claim 2
Dependent Claim
133 words
A circuit for the detection of software errors comprising: a timer circuit clocked by a clock pulse for providing an output when a predetermined period of time lapses; a control circuit for providing a sequence of data output values responsive to the clock pulse, comprising a counter responsive to said clock pulse, and a multiplexer; a comparator for comparing each one of said sequence of data output values from the control circuit with a data bus and for generating an output signal when the one of the data output values from the control circuit does not equal the corresponding one of the data input values from the data bus; and a decision circuit for generating an alarm signal when either the predetermined period of time lapses or the comparaator generates the output signal.
Claim 3
Dependent Claim
17 words
The circuit of claim 1 wherein said control circuit comprises a counter responsive to said clock pulse.
Claim 4
Dependent Claim
15 words
The circuit of claim 2 wherein said control circuit further comprises a read only memory.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-05-14 | 1993-11-13 | 1994-05-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-05-14 | 1997-11-13 | 1998-05-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-05-14 | 2001-11-13 | 2002-05-15 | $7700.00 | Window Closed / Lapsed |