US4926383A
Expired / Lapsed
US
⏱️ 0.0 years remaining
BiCMOS write-recovery circuit
Assignee: Fairchild Semiconductor Corp
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Filing: 1988-02-02
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Granted: 1990-05-15
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Expires: 2008-02-02
Abstract
Abstract A BiCMOS write-recovery method and circuit for recovering bit lines in a digital memory system provides approximately 1 nS recovery time and allows a 256K BiCMOS SRAM to achieve 10 nS access time. All bit lines in the memory system connected to a column not being read are held at a high potential, approximately equal to the upper power supply. During a write, one bit line is pulled low and its complementary bit line is clamped with a bipolar transistor to an intermediate potential, thereby preloading the complementary bit line. Following a write, the bit line that was pulled low is pulled up with a bipolar transistor to the intermediate voltage. Simultaneously, the bit line and the complementary bit line are shunted together, then returned to the high potential. Undesired bootstrap capacitance effects in the bipolar transistors are minimized by connecting a plurality of pull-up transistors in parallel, and by feeding the clamping transistors with low impedance drivers.
Inventors
- 👤 Robert A. Kertis
- 👤 Douglas D. Smith
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 08:25
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/413; G11C11/417; G11C11/419
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
176 words
In a memory system which includes a memory cell (16), first and second bit lines (18A, 20A) connected to the memory cell, means (120, 130), coupled to said first and second bit lines, for writing information into the memory cell by decreasing the voltage on a selected one of the first and second bit lines, and reading means (8), coupled to said first and second bit lines, for reading information from the memory cell through the voltage differential between said bit lines, a write-recovery circuit comprising: first and second clamping means (170, 190), coupled to said first and second bit lines, respectively, for selectively clamping the nonselected bit line to a first intermediate voltage while the information is being written; and first and second pull-up means (80, 90), coupled to said first and second bit lines, respectively, for selectively coupling the selected bit line to the first intermediate voltage after the information has been written, whereby after information is written into said cell, said bit lines have a low voltage differential and can be read quickly.
Claim 2
Dependent Claim
176 words
In a memory system which includes a memory cell (16), first and second bit lines (18A, 20A) connected to the memory cell, means (120, 130), coupled to said first and second bit lines, for writing information into the memory cell by decreasing the voltage on a selected one of the first and second bit lines, and reading means (8), coupled to said first and second bit lines, for reading information from the memory cell through the voltage differential between said bit lines, a write-recovery circuit comprising: first and second clamping means (170, 190), coupled to said first and second bit lines, respectively, for selectively clamping the nonselected bit line to a first intermediate voltage while the information is being written; and first and second pull-up means (80, 90), coupled to said first and second bit lines, respectively, for selectively coupling the selected bit line to the first intermediate voltage after the information has been written, whereby after information is written into said cell, said bit lines have a low voltage differential and can be read quickly.
Claim 3
Dependent Claim
27 words
A circuit as in claim 1 wherein each of said first and second clamping means and said first and second pull-up means comprises a separate bipolar transistor.
Claim 4
Dependent Claim
50 words
A circuit as in claim 2 wherein each clamping transistor has an input terminal, and further including means for connecting the input terminals of said first and second clamping transistors to the input terminals of a plurality of additional clamping transistors for a plurality of additional memory cells in parallel.
Claim 5
Dependent Claim
29 words
A circuit as in claim 1 further including means for interconnecting the bit lines of cells other than the cell into which information is written to a first voltage.
Claim 6
Dependent Claim
26 words
A circuit as in claim 1 further including means for shunting the first bit line to the second bit line while the information is being read.
Claim 7
Dependent Claim
14 words
A circuit as in claim 5 wherein the means for shunting comprises a transistor.
Claim 8
Dependent Claim
25 words
A circuit as in claim 1 further including third means for connecting the bit lines to a first voltage while the information is being read.
Claim 9
Dependent Claim
15 words
A circuit as in claim 7 wherein the third means for connecting comprises a transistor.
Claim 10
Dependent Claim
13 words
The circuit of claim 6 wherein said shunting transistor is an MOS transistor.
Claim 11
Dependent Claim
57 words
The circuit of claim 1 wherein said first and second clamping means are first and second bipolar transistors, and further comprising first and second MOS transistors, having gates coupled to the bases of said first and second bipolar transistors, respectively, for providing a path from said intermediate voltage and such bipolar transistor to a low voltage level.
Claim 12
Dependent Claim
54 words
The circuit of claim 1 further comprising first and second load transistors coupling said first and second bit lines, respectively, to a supply voltage, said first and second load transistors having control electrodes coupled to a first control line, said first and second pull-up means having control electrodes coupled to a second control line.
Claim 13
Dependent Claim
314 words
In a BiMOS static memory system which includes a static MOS memory cell, first and second bit lines connected to the memory cell, first and second MOS load transistors coupling said first and second bit lines to a voltage supply, writing means, coupled to said first and second bit lines, for writing information into the memory cell by decreasing the voltage on a selected one of the first and second bit lines, and reading means, coupled to said first and second bit lines, for reading information from the cell through the voltage differential between said bit lines, the write-recovery circuit comprising: first and second bipolar clamping transistors, each having a first electrode coupled to a supply voltage and a second electrode coupled to one of said first and second bit lines, and a base coupled to one of first and second control lines; first and second MOS clamping transistors, each having a first electrode coupled to one of said second and first bit lines, respectively, a second electrode coupled to a low voltage and a gate electrode coupled to said first and second control lines, respectively; third and fourth bipolar pull-up transistors, each having a first electrode coupled to said voltage supply, a second electrode coupled to one of said first and second bit lines, and a base electrode coupled to a third control line; and an MOS shunt transistor coupling said first and second bit lines together; whereby, while said information is being written, a non-selected bit line is pulled up to near said supply voltage by one of said bipolar and MOS clamping transistors and, after information is written into said memory cell, the selected bit line is pulled up to near said supply voltage by one of said bipolar pull-up transistors, such that the voltage level of said first and second bit lines are substantially equal after the writing of information.
Claim 14
Dependent Claim
314 words
In a BiMOS static memory system which includes a static MOS memory cell, first and second bit lines connected to the memory cell, first and second MOS load transistors coupling said first and second bit lines to a voltage supply, writing means, coupled to said first and second bit lines, for writing information into the memory cell by decreasing the voltage on a selected one of the first and second bit lines, and reading means, coupled to said first and second bit lines, for reading information from the cell through the voltage differential between said bit lines, the write-recovery circuit comprising: first and second bipolar clamping transistors, each having a first electrode coupled to a supply voltage and a second electrode coupled to one of said first and second bit lines, and a base coupled to one of first and second control lines; first and second MOS clamping transistors, each having a first electrode coupled to one of said second and first bit lines, respectively, a second electrode coupled to a low voltage and a gate electrode coupled to said first and second control lines, respectively; third and fourth bipolar pull-up transistors, each having a first electrode coupled to said voltage supply, a second electrode coupled to one of said first and second bit lines, and a base electrode coupled to a third control line; and an MOS shunt transistor coupling said first and second bit lines together; whereby, while said information is being written, a non-selected bit line is pulled up to near said supply voltage by one of said bipolar and MOS clamping transistors and, after information is written into said memory cell, the selected bit line is pulled up to near said supply voltage by one of said bipolar pull-up transistors, such that the voltage level of said first and second bit lines are substantially equal after the writing of information.
References Cited (Backward Citations)
US4078261A
Cited
US4791613A
Cited
US4768168A
Cited
US4740926A
Cited
US4685086A
Cited
US4744059A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-05-14 | 1993-11-13 | 1994-05-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-05-14 | 1997-11-13 | 1998-05-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-05-14 | 2001-11-13 | 2002-05-15 | $7700.00 | Window Closed / Lapsed |