US4768168A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Memory circuit having an improved writing scheme
Assignee: NEC Corp
•
Filing: 1986-03-18
•
Granted: 1988-08-30
•
Expires: 2006-03-18
Abstract
Abstract An improved memory circuit having a fast write speed is disclosed. A first control signal is generated when a first period of time has elapsed from the initiation of an access cycle, in a fixed timing both in a read operation and a write operation. A second control signal for enabling a data input circuit when a second shorter period has elapsed from the initiation of the access cycle only in a write operation. A data transfer between a selected bit line and a bus line is performed when at least one of the first and second control signals.
Inventors
- 👤 Takayuki Watanabe
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 15:08
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1078; G11C7/1084
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
317 words
A memory circuit comprising a plurality of word lines, a plurality pairs of bit lines, a plurality of static memory cells each coupled to one of the word lines and a pair of bit lines, a pair of bus lines, a plurality of pairs of transfer gates, each pair of transfer gates being coupled between each pair of bit lines and said pair of bus lines, an input data buffer circuit for operatively supplying sid pair of bus lines with input data in a write mode, an output circuit coupled to said pair of bus lines for outputting a read signal in a read mode, a bit line selection circuit for operatively enabling one pair of transfer gates thereby to transfer data at said pair of bus lines to a selected pair of bit lines through the enabled pair of transfer gates in the write mode and transfer data at the selected pair of bit lines to the pair of bus lines through the enabled pair of transfer gates in the read mode, means for generating a first control signal when a first period of time has elapsed from the initiation of an access cycle in the read mode and the write mode, means for generating a second control signal when a second period of time has elapsed from said initiation of the access cycle only in the write mode, said second period being shorter than said first period, means responsive to said second control signal for enabling said input data buffer circuit, and a column control circuit for enabling said bit line selection circuit in response to said first control signal in the read mode and in response to said second control signal in the write mode, whereby the selection of the transfer gates is achieved with a shorter delay time from the initiation of access cycle in the write mode than in the read mode.
Claim 2
Dependent Claim
317 words
A memory circuit comprising a plurality of word lines, a plurality pairs of bit lines, a plurality of static memory cells each coupled to one of the word lines and a pair of bit lines, a pair of bus lines, a plurality of pairs of transfer gates, each pair of transfer gates being coupled between each pair of bit lines and said pair of bus lines, an input data buffer circuit for operatively supplying sid pair of bus lines with input data in a write mode, an output circuit coupled to said pair of bus lines for outputting a read signal in a read mode, a bit line selection circuit for operatively enabling one pair of transfer gates thereby to transfer data at said pair of bus lines to a selected pair of bit lines through the enabled pair of transfer gates in the write mode and transfer data at the selected pair of bit lines to the pair of bus lines through the enabled pair of transfer gates in the read mode, means for generating a first control signal when a first period of time has elapsed from the initiation of an access cycle in the read mode and the write mode, means for generating a second control signal when a second period of time has elapsed from said initiation of the access cycle only in the write mode, said second period being shorter than said first period, means responsive to said second control signal for enabling said input data buffer circuit, and a column control circuit for enabling said bit line selection circuit in response to said first control signal in the read mode and in response to said second control signal in the write mode, whereby the selection of the transfer gates is achieved with a shorter delay time from the initiation of access cycle in the write mode than in the read mode.
Claim 3
Dependent Claim
45 words
The memory circuit according to claim 1, in which said column control circuit includes a column decoder, a first NOR gate receiving said first and second control signals, and a second NOR gate receiving the outputs of said column decoder and said first NOR gate.
Claim 4
Dependent Claim
31 words
The memory circuit according to claim 1, further comprising a sense amplifier provided for each pair of bit lines and means for enabling said sense amplifier only in the read mode.
Claim 5
Dependent Claim
294 words
A memory circuit comprising a plurality of word lines, a plurality of bit lines defining columns of said memory, a plurality of memory cells each coupled to one of said word lines and one of said bit lines, a bus line, a plurality of transfer gates each coupled between each one of said bit lines and said bus line, an data input circuit for operatively supplying said bus line with input data in a write mode, a read circuit coupled to said bus line for operatively generating a read-out signal in response to data at said bus line in a read mode, selection means coupled to said plurality of transfer gates for operatively enabling one of said transfer gates thereby to transfer data at said bus line through the enabled transfer gate to a selected bit line in the write mode and to transfer data at a selected bit line to said bus line through the enabled transfer gate in the read mode, means for generating a first control signal when a first period of time has elapsed from an initiation of an access cycle in the read mode and the write mode, means for generating a second control signal when a second period of time has elapsed from the initiation of the access cycle only in the write mode, means responsive to said second control signal for enabling said data input circuit, and a control circuit for enabling said selection means in response to said first control signal in the read mode and in response to said second control signal in the write mode, whereby the selection of said transfer gates is achieved with a shorter delay time from the initiation of access cycle in the write mode than in the read mode.
Claim 6
Dependent Claim
294 words
A memory circuit comprising a plurality of word lines, a plurality of bit lines defining columns of said memory, a plurality of memory cells each coupled to one of said word lines and one of said bit lines, a bus line, a plurality of transfer gates each coupled between each one of said bit lines and said bus line, an data input circuit for operatively supplying said bus line with input data in a write mode, a read circuit coupled to said bus line for operatively generating a read-out signal in response to data at said bus line in a read mode, selection means coupled to said plurality of transfer gates for operatively enabling one of said transfer gates thereby to transfer data at said bus line through the enabled transfer gate to a selected bit line in the write mode and to transfer data at a selected bit line to said bus line through the enabled transfer gate in the read mode, means for generating a first control signal when a first period of time has elapsed from an initiation of an access cycle in the read mode and the write mode, means for generating a second control signal when a second period of time has elapsed from the initiation of the access cycle only in the write mode, means responsive to said second control signal for enabling said data input circuit, and a control circuit for enabling said selection means in response to said first control signal in the read mode and in response to said second control signal in the write mode, whereby the selection of said transfer gates is achieved with a shorter delay time from the initiation of access cycle in the write mode than in the read mode.
Claim 7
Dependent Claim
44 words
The memory circuit according to claim 4, in which said control circuit includes a column decoder, a first NOR gate receiving said first and second control signals, and a second NOR gate receiving the outputs of said column decoder and said first NOR gate.
Claim 8
Dependent Claim
19 words
The memory circuit according to claim 4, in which each of said memory cells is of a static type.
Claim 9
Dependent Claim
28 words
The memory circuit according to claim 4, further comprising a sense amplifier provided for each column and means for enabling said sense amplifier only in a read operation.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-08-30 | 1992-02-29 | 1992-08-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-08-30 | 1996-02-29 | 1996-08-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-08-30 | 2000-02-29 | 2000-08-30 | $7700.00 | Window Closed / Lapsed |