Apparatus and method for reducing write recovery time in a random access memory

Claim 2

In a memory including an array of memory cells organized into a plurality of memory words, and including means responsive to a write enable signal for writing a data word appearing at memory input data lines to a selected memory word when said write enable signal is in a first state, and for coupling the data word stored in a selected memory word to memory output data lines when said write enable signal is in a second state, said means for coupling a data word stored in a selected memory word to said output data lines including sense amplifier means for amplifying said stored data word, an apparatus for reducing the write recovery time of said memory comprising: means responsive to said write enable signal being in said first state for decoupling said data word coupling means from said output data lines; second data path means for coupling said data word appearing at said input data lines to said output data lines beginning at a time at least by when said write enable signal changes from said first state to said second state; and means for overriding said second data path means when the output of said sense amplifier means matches the data state of the data word stored in said selected memory word.

Claim 3

The apparatus of claim 1 wherein said second data path means comprises: cache memory means; means for storing said data word in said cache memory means; and means for causing the data word stored in said cache memory means to be coupled to said output data lines when said write enable signal changes from said first state to said second state.

Claim 4

The apparatus of claim 2 wherein said cache memory means comprises a plurality of memory bits, each bit comprising first and second transistors; means for connecting said first and second transistors in a cross-coupled configuration; and biasing means for maximizing the switching speed of said first and second transistors.

Claim 5

The apparatus of claim 1 wherein said means for decoupling said data coupling means from said output data lines comprises transistor switch means responsive to said write enable signal being in said first state for decoupling the amplified stored data word output by said sense amplifier means from said output data lines.

Claim 6

The apparatus of claim 1 wherein said second data path means comprises: cache memory means; transistor switch means responsive to said write enable signal being in said first state for coupling said data word appearing at said memory input data lines to said output data lines and to said cache memory means, said cache memory means acting in response thereto to reflect the state of said data word; and means responsive to when said write enable signal changes state from said first state to said second state for coupling the data state of said cache memory means to said output data lines and for decoupling said transistor switch means.

Claim 7

The apparatus of claim 1 wherein said means for overriding said second data path means comprises means responsive to said write enable signal being in said second state for coupling the output of said sense amplifier means to said output data lines after said selected memory word has reached a steady state.

Claim 8

In a memory including an array of memory cells organized into a plurality of memory words, and including means for writing data appearing at memory input data lines to a selected memory word when a write enable signal is generated, and for reading out to memory output data lines the data stored in a selected memory word when said write enable signal is removed, said means for reading out data stored in a selected memory word to said output data lines including sense amplifier means for amplifying said stored data, an apparatus for reducing the write recovery time of said memory during a write operation comprising: cache memory means, means responsive to the generation of said write enable signal for decoupling said data read out means from said output data lines, for storing in said cache memory means the data state of data being stored in a selected said memory word, and for coupling the data stored in said cache memory means to said output data lines beginning at a time at least by when said write enable signal is removed; and means responsive to the removal of said write enable signal for overriding said cache memory coupling means when the output of said sense amplifier means matches the data state of the data written into said selected memory word.

Claim 9

In a memory including an array of memory cells organized into a plurality of memory words, and including means for writing data appearing at memory input data lines to a selected memory word when a write enable signal is generated, and for reading out to memory output data lines the data stored in a selected memory word when said write enable signal is removed, said means for reading out data stored in a selected memory word to said output data lines including sense amplifier means for amplifying said stored data, an apparatus for reducing the write recovery time of said memory during a write operation comprising: cache memory means, means responsive to the generation of said write enable signal for decoupling said data read out means from said output data lines, for storing in said cache memory means the data state of data being stored in a selected said memory word, and for coupling the data stored in said cache memory means to said output data lines beginning at a time at least by when said write enable signal is removed; and means responsive to the removal of said write enable signal for overriding said cache memory coupling means when the output of said sense amplifier means matches the data state of the data written into said selected memory word.

Claim 10

In a memory including an array of memory cells and a plurality of word and bit lines for selectively addressing each said cell for either writing a desired data state to a selected cell responsive to the existance of a write enable signal, said data state being coupled to said cell on its associated bit line, or for reading out the current data state stored by said selected cell responsive to the absense of said write enable signal, said data state appearing on the associated bit line of said cell, each bit line further including means for amplifying said data state during read out and for coupling the amplified data state to a corresponding output data line, an apparatus for reducing the write recovery time of a memory cell into which a selected data state is being written, comprising: means responsive to the existance of said write enable signal for decoupling the bit line associated with the selected memory cell into which a data state is being written from said corresponding output data line; cache memory means; means responsive to the existance of said write enable signal for storing in said cache memory means the data state being written into said selected memory cell; means for coupling said data state stored in said cache memory means to the data output line corresponding to said selected memory cell in response to the removal of said write enable signal; and means for overriding said data state coupling means when the memory cell into which said selected data state is being written reaches a steady state condition.

Claim 11

In a memory including an array of memory cells and a plurality of word and bit lines for selectively addressing each said cell for either writing a desired data state to a selected cell responsive to the existance of a write enable signal, said data state being coupled to said cell on its associated bit line, or for reading out the current data state stored by said selected cell responsive to the absense of said write enable signal, said data state appearing on the associated bit line of said cell, each bit line further including means for amplifying said data state during read out and for coupling the amplified data state to a corresponding output data line, an apparatus for reducing the write recovery time of a memory cell into which a selected data state is being written, comprising: means responsive to the existance of said write enable signal for decoupling the bit line associated with the selected memory cell into which a data state is being written from said corresponding output data line; cache memory means; means responsive to the existance of said write enable signal for storing in said cache memory means the data state being written into said selected memory cell; means for coupling said data state stored in said cache memory means to the data output line corresponding to said selected memory cell in response to the removal of said write enable signal; and means for overriding said data state coupling means when the memory cell into which said selected data state is being written reaches a steady state condition.

Claim 12

The apparatus of claim 8 wherein said means for decoupling the bit line associated with said selected memory cell comprises transistor switch means responsive to the existance of said write enable signal for decoupling the amplified data state output of said bit line amplifying means from said corresponding output data line.

Claim 13

The apparatus of claim 8 wherein said cache memory means comprises first and second transistors; means for connecting said first and second transistors in a cross-coupled configuration such that a data state input to said first and second transistors is stored thereby; and means for biasing said first and second transistors to maximize their switching speed.

Claim 14

The apparatus of claim 8 wherein said means for storing the data state being written into said selected memory cell in said cache memory means comprises transistor switch means for coupling said data state being written to said memory cell to said cache memory means responsive to the existance of said write enable signal.

Claim 15

The apparatus of claim 8 wherein said means for overriding said data state coupling means comprises means responsive to the absence of said write enable signal for coupling the output of said sense amplifier means to said output data line after said corresponding selected memory cell has reached a steady state.

Claim 16

In a memory including an array of memory cells and a plurality of word and bit lines for selectively addressing each said cell for either writing a desired data state to a selected cell responsive to the existance of a write enable signal, said data state being coupled to said cell on its associated bit line, or for reading out the current data state stored by said selected cell responsive to the absense of said write enable signal, said data state appearing on the associated bit line of said cell, each bit line further including means for amplifying said data state during read out and for coupling the amplified data state to a corresponding output data line, a method for reducing the write recovery time of a memory cell into which a selected data state is being written, comprising the steps of: detecting the existance of said write enable signal; decoupling the bit line associated with the selected memory cell into which said data state is being written from said corresponding output data line in response to said detection of said write enable signal; coupling said data state being written to said output data lines over a second data path; storing said data state being written in a fast cache memory whose switching speed is fast with respect to said memory cell; detecting the absense of said write enable signal; coupling said data state stored in said cache memory means to said output data line corresponding to said selected memory cell in response to said detection of the absense of said write enable signal; and recoupling said bit line associated with said selected memory cell to said corresponding output data line when the memory cell into which selected data state is being written reaches a steady state condition.

Claim 17

In a memory including an array of memory cells and a plurality of word and bit lines for selectively addressing each said cell for either writing a desired data state to a selected cell responsive to the existance of a write enable signal, said data state being coupled to said cell on its associated bit line, or for reading out the current data state stored by said selected cell responsive to the absense of said write enable signal, said data state appearing on the associated bit line of said cell, each bit line further including means for amplifying said data state during read out and for coupling the amplified data state to a corresponding output data line, a method for reducing the write recovery time of a memory cell into which a selected data state is being written, comprising the steps of: detecting the existance of said write enable signal; decoupling the bit line associated with the selected memory cell into which said data state is being written from said corresponding output data line in response to said detection of said write enable signal; coupling said data state being written to said output data lines over a second data path; storing said data state being written in a fast cache memory whose switching speed is fast with respect to said memory cell; detecting the absense of said write enable signal; coupling said data state stored in said cache memory means to said output data line corresponding to said selected memory cell in response to said detection of the absense of said write enable signal; and recoupling said bit line associated with said selected memory cell to said corresponding output data line when the memory cell into which selected data state is being written reaches a steady state condition.