Patent FR972246A successfully refreshed from Google Patents.
Patent US4926369A successfully refreshed from Google Patents.
US4926369A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Leading 0/1 anticipator (LZA)
Assignee: International Business Machines Corp
•
Filing: 1988-10-07
•
Granted: 1990-05-15
•
Expires: 2008-10-07
Abstract
Abstract A method and system for performing a leading 0/1 anticipation (LZA) in parallel with the floating-point addition of two operands (A and B) in a computer to significantly reduce the Addition-Normalization time. A combinational network is used to process appropriate XOR (P), AND (G) and NOR (Z) state signals resulting from the comparison of the bits in corresponding bit positions of the operands (A and B), starting with the most significant bit (MSB) side of the addition. The state of the initial state signal is detected and shift amount signals are produced and counted for each successive state signal detected, as long as the state remains TRUE. When the state becomes NOT TRUE, adjustments are made depending on the initial state and the successive state, and production of the shift amount signals is halted and an adjustment signal is produced. To determine the exponent of the sum of the floating-point addition, the shift amount count is summed with the adjustment signal. The latter sum will be the exponent of the sum of the operands thus providing a normalized result. The adjustment signal may be based on the CARRY at the NOT TRUE bit position, and the state at the NOT TRUE position may be used to determine whether the result of the addition is positive or negative. In addition to a serial network, an implementing network of a parallel form which accepts appropriate state inputs as blocks of n bits in length, is disclosed, along with certain special implementations.
Inventors
- 👤 Erdem Hokenek
- 👤 Robert K. Montoye
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 11:22
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/74; G06F5/00; G06F5/01; G06F5/012
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
305 words
A method of normalizing the result of a floating point addition in a computer by carrying out leading zero processing in parallel with the addition of the operands (A and B), comprising the steps of: starting with the most significant bit (MSB) side of the operands, comparing the bits in corresponding bit positions of the operands (A and B), and producing appropriate XOR (P), AND (G), and NOR (Z) state signals in accordance with the comparisons; detecting the state of the initial state signal and producing a shift amount signal indicating a shift amount for each successive state signal produced; when said state of said initial state signal is G or Z, halting the production of said shift amount signals when the state of a subsequently produced state signal first becomes NOT TRUE with respect to said state of said initial state signal indicating a second state when said state of said initial state signal is P and the state of a subsequently produced state signal first becomes NOT TRUE with respect to said state of said initial state signal indicating a second state (G or Z), which state at the NOT TRUE bit position is followed by a state signal of the third state (Z or G), then continuing to produce shift amount signals for each successive state signal produced as long as said third state remains TRUE and halting the production of said shift amount signals when the third state becomes NOT TRUE; otherwise, when said initial state is P, halting the shift signals at one bit position following the NOT TRUE bit position; producing an adjustment signal when the production of said shift amount signals is halted; and counting the shift amounts and summing the count with said adjustment signal to determine the exponent of the sum of the floating point addition.
Claim 2
Independent Claim
305 words
A method of normalizing the result of a floating point addition in a computer by carrying out leading zero processing in parallel with the addition of the operands (A and B), comprising the steps of: starting with the most significant bit (MSB) side of the operands, comparing the bits in corresponding bit positions of the operands (A and B), and producing appropriate XOR (P), AND (G), and NOR (Z) state signals in accordance with the comparisons; detecting the state of the initial state signal and producing a shift amount signal indicating a shift amount for each successive state signal produced; when said state of said initial state signal is G or Z, halting the production of said shift amount signals when the state of a subsequently produced state signal first becomes NOT TRUE with respect to said state of said initial state signal indicating a second state when said state of said initial state signal is P and the state of a subsequently produced state signal first becomes NOT TRUE with respect to said state of said initial state signal indicating a second state (G or Z), which state at the NOT TRUE bit position is followed by a state signal of the third state (Z or G), then continuing to produce shift amount signals for each successive state signal produced as long as said third state remains TRUE and halting the production of said shift amount signals when the third state becomes NOT TRUE; otherwise, when said initial state is P, halting the shift signals at one bit position following the NOT TRUE bit position; producing an adjustment signal when the production of said shift amount signals is halted; and counting the shift amounts and summing the count with said adjustment signal to determine the exponent of the sum of the floating point addition.
Claim 3
Dependent Claim
26 words
A method as in claim 1, wherein said adjustment signal is determined by the CARRY at the bit position at which the shift signals are halted.
Claim 4
Dependent Claim
37 words
A method as in claim 1, further comprising the step of using the state at the bit position at which the shift signals are halted to determine whether the result of the addition is positive or negative.
Claim 5
Dependent Claim
368 words
Apparatus for normalizing the result of a floating point addition in a computer by carrying out leading zero processing in parallel with the addition of the operands (A and B), comprising: means for comparing the bits in corresponding bit positions of the operands (A and B) and producing XOR (P), AND (G), and NOR (Z) state signals in accordance therewith; means for actuating said comparing means to start with the most significant bit (MSB) side of the operands and produce appropriate XOR (P), AND (G), and NOR (Z) state signals by comparing the bits in corresponding bit positions of the operands (A and B); means for detecting the state of the initial state signal produced; means for outputting a shift amount signal indicating a shift amount for each successive state signal produced; means, actuated when said state of said initial state signal is G or Z, for halting the outputting of said shift amount signals by said outputting means when the state of a subsequently produced state signal first becomes NOT TRUE with respect to said state of said initial state signal indicating a second state means, actuated when said state of said initial state signal is P and the state of a subsequently produced state signal first becomes NOT TRUE with respect to said state of said initial state signal indicating a second state (G or Z), which state at the NOT TRUE bit position is followed by a state signal of the third state (Z or G), for halting the outputting of said shift amount signals by said outputting means when the third state becomes NOT TRUE; means, actuated when said initial state is P and the second state (G or Z) at the NOT TRUE bit position is not followed by a state signal of the third state, for halting the outputting of shift signals by said outputting means at one bit position following the NOT TRUE bit position; means for producing an adjustment signal when the outputting of said shift amount signals is halted; and means for counting the shift amount signals and summing the shift amount count with the adjustment signal to determine the exponent of the sum of the floating point addition.
Claim 6
Dependent Claim
368 words
Apparatus for normalizing the result of a floating point addition in a computer by carrying out leading zero processing in parallel with the addition of the operands (A and B), comprising: means for comparing the bits in corresponding bit positions of the operands (A and B) and producing XOR (P), AND (G), and NOR (Z) state signals in accordance therewith; means for actuating said comparing means to start with the most significant bit (MSB) side of the operands and produce appropriate XOR (P), AND (G), and NOR (Z) state signals by comparing the bits in corresponding bit positions of the operands (A and B); means for detecting the state of the initial state signal produced; means for outputting a shift amount signal indicating a shift amount for each successive state signal produced; means, actuated when said state of said initial state signal is G or Z, for halting the outputting of said shift amount signals by said outputting means when the state of a subsequently produced state signal first becomes NOT TRUE with respect to said state of said initial state signal indicating a second state means, actuated when said state of said initial state signal is P and the state of a subsequently produced state signal first becomes NOT TRUE with respect to said state of said initial state signal indicating a second state (G or Z), which state at the NOT TRUE bit position is followed by a state signal of the third state (Z or G), for halting the outputting of said shift amount signals by said outputting means when the third state becomes NOT TRUE; means, actuated when said initial state is P and the second state (G or Z) at the NOT TRUE bit position is not followed by a state signal of the third state, for halting the outputting of shift signals by said outputting means at one bit position following the NOT TRUE bit position; means for producing an adjustment signal when the outputting of said shift amount signals is halted; and means for counting the shift amount signals and summing the shift amount count with the adjustment signal to determine the exponent of the sum of the floating point addition.
Claim 7
Dependent Claim
30 words
Apparatus as in claim 4, wherein said adjustment signal producing means produces an adjustment signal determined by the CARRY at the bit position at which the shift signals are halted.
Claim 8
Dependent Claim
35 words
Apparatus as in claim 4, further comprising means for using the state at the bit position at which the shift signals are halted to determine whether the result of the addition is positive or negative.
Claim 9
Dependent Claim
344 words
Apparatus for normalizing the result of a floating point addition in a computer by carrying out the leading zero detection (LZD) in parallel with the addition of the operands (A and B) to provide a leading zero anticipation (LZA), comprising: means for sequentially comparing the bits in corresponding bit positions of the operands (A and B) being added and for producing appropriate XOR (P), AND (G) and NOR (Z) state signals resulting from the comparing, starting with the most significant bit (MSB) side of the addition; means for detecting the state of the initial state signal produced and for detecting when said state becomes NOT TRUE; means for outputting a shift amount signal for each successive state signal produced; means for halting the outputting of said shift amount signals by said outputting means; means, responsive to said detecting means, for actuating said halting means to halt the outputting of said shift amount signals by said outputting means when said initial state is G or Z and said state becomes NOT TRUE; means, responsive to said detecting means, for actuating said halting means to halt the outputting of said shift amount signals by said outputting means when said initial state is P and the second state (G or Z) at the NOT TRUE bit position is followed by a state signal of the third state, and the third state becomes NOT TRUE; means, responsive to said detecting means, for actuating said halting means to halt the outputting of said shift amount signals by said outputting means at one bit position following the NOT TRUE position when said initial state is P and the second state (G or Z) at the NOT TRUE bit position is not followed by a state signal of the third state; means for producing an adjustment signal when the outputting of said shift amount signals is halted; and means for counting said shift amount signals and summing the count with said adjustment signal to determine the exponent of the sum of the floating point addition of the operands (A and B).
Claim 10
Dependent Claim
344 words
Apparatus for normalizing the result of a floating point addition in a computer by carrying out the leading zero detection (LZD) in parallel with the addition of the operands (A and B) to provide a leading zero anticipation (LZA), comprising: means for sequentially comparing the bits in corresponding bit positions of the operands (A and B) being added and for producing appropriate XOR (P), AND (G) and NOR (Z) state signals resulting from the comparing, starting with the most significant bit (MSB) side of the addition; means for detecting the state of the initial state signal produced and for detecting when said state becomes NOT TRUE; means for outputting a shift amount signal for each successive state signal produced; means for halting the outputting of said shift amount signals by said outputting means; means, responsive to said detecting means, for actuating said halting means to halt the outputting of said shift amount signals by said outputting means when said initial state is G or Z and said state becomes NOT TRUE; means, responsive to said detecting means, for actuating said halting means to halt the outputting of said shift amount signals by said outputting means when said initial state is P and the second state (G or Z) at the NOT TRUE bit position is followed by a state signal of the third state, and the third state becomes NOT TRUE; means, responsive to said detecting means, for actuating said halting means to halt the outputting of said shift amount signals by said outputting means at one bit position following the NOT TRUE position when said initial state is P and the second state (G or Z) at the NOT TRUE bit position is not followed by a state signal of the third state; means for producing an adjustment signal when the outputting of said shift amount signals is halted; and means for counting said shift amount signals and summing the count with said adjustment signal to determine the exponent of the sum of the floating point addition of the operands (A and B).
Claim 11
Dependent Claim
35 words
Apparatus as in claim 7, further comprising: means for using the state at the bit position at which the shift signals are halted to determine whether the result of the addition is positive or negative.
Claim 12
Dependent Claim
40 words
Apparatus as in claim 7, further comprising: means, responsive to said detecting means, for actuating said adjustment signal producing means to produce an adjustment signal determined by the CARRY at the bit position at which the shift signals are halted.
Claim 13
Independent Claim
274 words
A method for normalizing the result of a floating point addition in a computer by carrying out the leading zero detection (LZD) in parallel with the addition of the operands (A and B) to provide a leading zero anticipation (LZA), comprising the steps of: sequentially comparing the bits in corresponding bit positions of the operands (A and B) being added and producing appropriate XOR (P), AND (G) and NOR (Z) state signals resulting from the comparing, starting with the most significant bit (MSB) side of the addition; detecting the state of the initial state signal produced and detecting when said state becomes NOT TRUE; outputting a shift amount signal for each successive state signal produced; halting the outputting of said shift amount signals if said initial state is G or Z, when said state becomes NOT TRUE; halting the outputting of said shift amount signals if said initial state is P and the second state (G or Z) at the NOT TRUE bit position is followed by a state signal of the third state, when the third state becomes NOT TRUE; halting the outputting of said shift amount signals at one bit position following the NOT TRUE position if said initial state is P, when the second state (G or Z) at the NOT TRUE bit position is not followed by a state signal of the third state; producing an adjustment signal when the outputting of said shift amount signals is halted; and counting said shift amount signals and summing the count with said adjustment signal to determine the exponent of the sum of the floating point addition of the operands (A and B).
Claim 14
Independent Claim
274 words
A method for normalizing the result of a floating point addition in a computer by carrying out the leading zero detection (LZD) in parallel with the addition of the operands (A and B) to provide a leading zero anticipation (LZA), comprising the steps of: sequentially comparing the bits in corresponding bit positions of the operands (A and B) being added and producing appropriate XOR (P), AND (G) and NOR (Z) state signals resulting from the comparing, starting with the most significant bit (MSB) side of the addition; detecting the state of the initial state signal produced and detecting when said state becomes NOT TRUE; outputting a shift amount signal for each successive state signal produced; halting the outputting of said shift amount signals if said initial state is G or Z, when said state becomes NOT TRUE; halting the outputting of said shift amount signals if said initial state is P and the second state (G or Z) at the NOT TRUE bit position is followed by a state signal of the third state, when the third state becomes NOT TRUE; halting the outputting of said shift amount signals at one bit position following the NOT TRUE position if said initial state is P, when the second state (G or Z) at the NOT TRUE bit position is not followed by a state signal of the third state; producing an adjustment signal when the outputting of said shift amount signals is halted; and counting said shift amount signals and summing the count with said adjustment signal to determine the exponent of the sum of the floating point addition of the operands (A and B).
Claim 15
Dependent Claim
37 words
A method as in claim 10, further comprising the step of: using the state at the bit position at which the shift signals are halted to determine whether the result of the addition is positive or negative.
Claim 16
Dependent Claim
29 words
A method as in claim 10, further comprising the step of: determining said adjustment signal by the CARRY at the bit position at which the shift signals are halted.
Claim 17
Dependent Claim
196 words
A combinational network for normalizing the result of a floating point addition in a computer by carrying out the leading zero processing in parallel with the addition of the operands (A and B), comprising: means for comparing the bits in corresponding bit positions of the operands (A and B) being added; means, starting with the most significant bit (MSB) side of the addition, for providing appropriate state inputs in the form of blocks of n bits in length, said inputs comprising Z 1 to Z n , P 1 to P n , and G 1 to G n state signals resulting from the comparing of the bits in corresponding bit positions by said comparing means; means responsive to said state inputs for producing intermediate state outputs comprising ZZ, PP, PZ, PG, and GG signals; means for ORing said intermediate state outputs and producing signals indicative of a shift count; means for creating an adjustment signal based on the bit position at the end of the shift count; means for summing the shift count with the adjustment signal to determine the exponent of the sum of the floating point addition of the operands (A and B).
Claim 18
Dependent Claim
196 words
A combinational network for normalizing the result of a floating point addition in a computer by carrying out the leading zero processing in parallel with the addition of the operands (A and B), comprising: means for comparing the bits in corresponding bit positions of the operands (A and B) being added; means, starting with the most significant bit (MSB) side of the addition, for providing appropriate state inputs in the form of blocks of n bits in length, said inputs comprising Z 1 to Z n , P 1 to P n , and G 1 to G n state signals resulting from the comparing of the bits in corresponding bit positions by said comparing means; means responsive to said state inputs for producing intermediate state outputs comprising ZZ, PP, PZ, PG, and GG signals; means for ORing said intermediate state outputs and producing signals indicative of a shift count; means for creating an adjustment signal based on the bit position at the end of the shift count; means for summing the shift count with the adjustment signal to determine the exponent of the sum of the floating point addition of the operands (A and B).
Claim 19
Dependent Claim
36 words
A network as in claim 13, further comprising means for using the state of the bit position at the end of the shift count to determine whether the result of the addition is positive or negative.
Claim 20
Independent Claim
188 words
A method using a combinational network for normalizing the result of a floating point addition in a computer by carrying out the leading zero processing in parallel with the addition of the operands (A and B), comprising the steps of: comparing the bits in corresponding bit positions of the operands (A and B) being added; starting with the most significant bit (MSB) side of the addition, providing appropriate state inputs in the form of blocks of n bits in length, said inputs comprising Z 1 to Z n , P 1 to P n , and G 1 to G n state signals resulting from the comparing of the bits in corresponding bit positions; producing intermediate state outputs comprising ZZ, PP, PZ, PG, and GG signals, in response to said state inputs; ORing said intermediate state outputs and producing signals indicative of a shift count; creating an adjustment signal based on the bit position at the end of said shift count; and summing said shift count with said adjustment signal to determine the exponent of the sum of the floating point addition of the operands (A and B).
Claim 21
Independent Claim
188 words
A method using a combinational network for normalizing the result of a floating point addition in a computer by carrying out the leading zero processing in parallel with the addition of the operands (A and B), comprising the steps of: comparing the bits in corresponding bit positions of the operands (A and B) being added; starting with the most significant bit (MSB) side of the addition, providing appropriate state inputs in the form of blocks of n bits in length, said inputs comprising Z 1 to Z n , P 1 to P n , and G 1 to G n state signals resulting from the comparing of the bits in corresponding bit positions; producing intermediate state outputs comprising ZZ, PP, PZ, PG, and GG signals, in response to said state inputs; ORing said intermediate state outputs and producing signals indicative of a shift count; creating an adjustment signal based on the bit position at the end of said shift count; and summing said shift count with said adjustment signal to determine the exponent of the sum of the floating point addition of the operands (A and B).
Claim 22
Dependent Claim
37 words
A method as in claim 15, further comprising the step of using the state of the bit position at the end of said shift count to determine whether the result of the addition is positive or negative.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-05-14 | 1993-11-13 | 1994-05-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-05-14 | 1997-11-13 | 1998-05-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-05-14 | 2001-11-13 | 2002-05-15 | $7700.00 | Window Closed / Lapsed |