Patent US4926237A successfully refreshed from Google Patents.
US4926237A
Expired / Lapsed
US
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Device metallization, device and method
Assignee: Motorola Solutions Inc
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Filing: 1988-04-04
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Granted: 1990-05-15
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Expires: 2008-04-04
Abstract
Abstract A semiconductor device, device metallization, and method are described. The device metallization, which is especially designed for submicron contact openings, includes titanium silicide to provide a low resistance contact to a device region, titanium nitride and sputtered tungsten to provide a diffusion barrier, etched back chemical vapor deposited tungsten for planarization, and aluminum or an aluminum alloy for interconnection.
Inventors
- 👤 Shih W. Sun
- 👤 Jen-Jiang Lee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 14:27
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/425; H10W20/45; H10W20/48
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
75 words
Metallization for contacting the silicon substrate of a semiconductor device comprising: titanium silicide in contact with selected portions of the silicon substrate; a layer of titanium nitride overlying said titanium silicide; a layer of insitu sputtered tungsten disposed on and in intimate contact with said titanium nitride; a localized layer of chemical vapor deposited tungsten overlying said layer of sputtered tungsten; and a patterned layer comprising aluminum contacting said layer of chemical vapor deposited tungsten.
Claim 2
Dependent Claim
75 words
Metallization for contacting the silicon substrate of a semiconductor device comprising: titanium silicide in contact with selected portions of the silicon substrate; a layer of titanium nitride overlying said titanium silicide; a layer of insitu sputtered tungsten disposed on and in intimate contact with said titanium nitride; a localized layer of chemical vapor deposited tungsten overlying said layer of sputtered tungsten; and a patterned layer comprising aluminum contacting said layer of chemical vapor deposited tungsten.
Claim 3
Dependent Claim
29 words
The metallization of claim 1 wherein said layer of titanium nitride and said layer of sputtered tungsten together have a thickness sufficient to prevent the diffusion of silicon therethrough.
Claim 4
Dependent Claim
81 words
Metallization for contacting the silicon substrate of a semiconductor device comprising: a silicide layer electrically contacting the silicon substrate; a diffusion barrier layer comprising insitu sputtered tungsten disposed on and in intimate contact with said silicide layer and preventing the diffusion of silicon therethrough; a planarizing plug of conductive material overlying said diffusion barrier layer; and a layer of interconnect metallization making selective electrical contact to said planarizing plug wherein said interconnect metallization comprises a material different from said conductive material.
Claim 5
Dependent Claim
81 words
Metallization for contacting the silicon substrate of a semiconductor device comprising: a silicide layer electrically contacting the silicon substrate; a diffusion barrier layer comprising insitu sputtered tungsten disposed on and in intimate contact with said silicide layer and preventing the diffusion of silicon therethrough; a planarizing plug of conductive material overlying said diffusion barrier layer; and a layer of interconnect metallization making selective electrical contact to said planarizing plug wherein said interconnect metallization comprises a material different from said conductive material.
Claim 6
Dependent Claim
21 words
The metallization of claim 3 wherein said silicide layer is selected from the group consisting of titanium silicide and cobalt silicide.
Claim 7
Dependent Claim
59 words
Metallization for contacting the silicon substrate of a semiconductor device comprising: a silicide layer electrically contacting the silicon substrate; a diffusion barrier layer of titanium nitride overlying said silicide layer and preventing the diffusion of silicon therethrough; a planarizing plug of conductive material overlying said diffusion barrier layer; and a layer of interconnect metallization selectively contacting said planarizing plug.
Claim 8
Dependent Claim
59 words
Metallization for contacting the silicon substrate of a semiconductor device comprising: a silicide layer electrically contacting the silicon substrate; a diffusion barrier layer of titanium nitride overlying said silicide layer and preventing the diffusion of silicon therethrough; a planarizing plug of conductive material overlying said diffusion barrier layer; and a layer of interconnect metallization selectively contacting said planarizing plug.
Claim 9
Dependent Claim
20 words
The metallization of claim 5 wherein said diffusion barrier further comprises a layer of sputtered tungsten overlying said titanium nitride.
Claim 10
Dependent Claim
14 words
The metallization of claim 5 wherein said planarizing layer comprises chemical vapor deposited tungsten.
Claim 11
Dependent Claim
11 words
The metallization of claim 5 wherein said planarizing layer comprises molybdenum.
Claim 12
Dependent Claim
19 words
The metallization of claim 8 wherein said layer of interconnect metallization comprises a material different from said conductive material.
Claim 13
Dependent Claim
92 words
A semiconductor device comprising: a silicon substrate including device regions; an insulating material overlying said substrate and having openings therethrough exposing selected portions of said device regions; titanium silicide formed on and electrically contacting said selected portions; a layer of titanium nitride overlying said titanium silicide; a layer of insitu sputtered tungsten disposed on and in intimate contact with said titanium nitride; a planarizing plug of chemically vapor deposited tungsten overlying said sputtered tungsten and substantially filling said opening; and a layer of patterned aluminum selectively contacting said chemically vapor deposited tungsten.
Claim 14
Dependent Claim
92 words
A semiconductor device comprising: a silicon substrate including device regions; an insulating material overlying said substrate and having openings therethrough exposing selected portions of said device regions; titanium silicide formed on and electrically contacting said selected portions; a layer of titanium nitride overlying said titanium silicide; a layer of insitu sputtered tungsten disposed on and in intimate contact with said titanium nitride; a planarizing plug of chemically vapor deposited tungsten overlying said sputtered tungsten and substantially filling said opening; and a layer of patterned aluminum selectively contacting said chemically vapor deposited tungsten.
Claim 15
Dependent Claim
13 words
The semiconductor device of claim 10 wherein said insulating material comprises boronphosphosilicate glass.
Claim 16
Dependent Claim
17 words
The semiconductor device of claim 10 wherein said openings have a diameter of less than 1 micrometer.
Claim 17
Dependent Claim
99 words
A semiconductor device comprising: a silicon substrate including device regions; an insulating material overlying said substrate and having openings therethrough exposing selected portions of said device regions; a silicide material formed on and electrically contacting said selected portions; a silicon diffusion barrier layer comprising a layer of titanium nitride and a layer of insitu sputtered tungsten disposed on and in intimate contact with said titanium nitride overlying said silicide layer; a conductive plug overlying said diffusion barrier layer and substantially filling said openings; and a patterned layer of aluminum overlying said insulating material and selectively contacting said conductive layer.
Claim 18
Dependent Claim
99 words
A semiconductor device comprising: a silicon substrate including device regions; an insulating material overlying said substrate and having openings therethrough exposing selected portions of said device regions; a silicide material formed on and electrically contacting said selected portions; a silicon diffusion barrier layer comprising a layer of titanium nitride and a layer of insitu sputtered tungsten disposed on and in intimate contact with said titanium nitride overlying said silicide layer; a conductive plug overlying said diffusion barrier layer and substantially filling said openings; and a patterned layer of aluminum overlying said insulating material and selectively contacting said conductive layer.
Claim 19
Dependent Claim
13 words
The semiconductor device of claim 13 wherein said device comprises an integrated circuit.
Claim 20
Dependent Claim
24 words
The semiconductor device of claim 13 wherein the top surface of said conductive material is substantially planar with the top of said insulating material.
Claim 21
Dependent Claim
23 words
The semiconductor device of claim 13 wherein said silicide comprises a material selected from the group consisting of titanium silicide and cobalt silicide.
Claim 22
Dependent Claim
19 words
The semiconductor device of claim 13 wherein said silicide comprises titanium silicide and said barrier material comprises titanium nitride.
Claim 23
Dependent Claim
23 words
The semiconductor device of claim 13 wherein said conductive plug is selected form the group consisting of chemical vapor deposited tungsten and molybdenum.
References Cited (Backward Citations)
US4164461A
Cited
EP0127281A1
Cited
US4582563A
Cited
JPS60227469A
Cited
US4624864A
Cited
US4751563A
Cited
JPS61174767A
Cited
JPS6257234A
Cited
JPS6261358A
Cited
US4818723A
Cited
US4823181A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-05-14 | 1993-11-13 | 1994-05-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-05-14 | 1997-11-13 | 1998-05-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-05-14 | 2001-11-13 | 2002-05-15 | $7700.00 | Window Closed / Lapsed |