Dynamic memory of the integrated circuit type

Claim 2

A dynamic memory of the integrated circuit type fabricated in a silicon wafer and provided with memory cells for capacative data storage, wherein said dynamic memory comprises: CMOS transistors fabricated in the CMOS technology for utilization as memory cells and provided with gate electrodes formed by a first level of deposited polysilicon and covered by a metallized layer to be utilized as a word line for the memory; means for capacitive storage by putting in opposition to each other, at a second and a third levels, two polysilicon layers, said second and third polysilicon layers being separated from each other and from the first level by insulating layers of silicon dioxide; regions of said second level polysilicon layer serving to form lower plate of capacitors of said cells, said regions of said second level polysilicon layer being separated by separations; data transfer lines formed of vacuum-deposited metal; the polysilicon layers of the second and third levels being formed so as to pass over the polysilicon layer of the first level wherein the transfer lines are superimposed over said separations but are not extended over said regions of said level polysilicon layer.

Claim 3

A memory according to claim 1, wherein the transfer lines comprise contact connections providing access to the transistor of a memory cell and wherein the polysilicon layer of the third level covers the entire wafer except for the regions of said wafer in which said contact connections are placed.

Claim 4

A memory according to claim 2, wherein the contact connections related to two memory cells for which the word lines are adjacent are combined in a single contact connection.

Claim 5

A memory according to claim 1, wherein the metallization of the polysilicon layer of the first level comprises a layer of tungsten polysilicides.

Claim 6

A memory according to claim 1, wherein the metal of the transfer lines in aluminum.

Claim 7

A memory according to claim 1, wherein the polysilicon layer of the second level is doped after deposition with the same impurities as those which have served to dope the drain and source regions of the transistors.

Claim 8

A memory according to claim 1, wherein said transistor with its drain implanted in a well in the perimeter of the drain regions is reduced in order to reduce the junction capacitance between said drain regions and a well in which said drains are implanted.

Claim 9

A dynamic energy of the integrated circuit type fabricated in a silicon wafer and provided with memory cells for capacitive data storage, wherein said dynamic memory comprises: CMOS transistors fabricated in the CMOS technology for utilization as memory cells and provided with gate electrodes formed by a first level of deposited polysilicon and covered by a metallized layer to be utilized as a word line for the memory; means for capacitive storage by putting in opposition to each other, at a second and a third levels, two polysilicon layers, said second and third level polysilicon layers being separated from each other and from the first level by insulating layers of silicon oxide; regions of said second level polysilicon layer serving to form lower plates of capacitors of said cells, said regions of said second level polysilicon layer being separated by separations; data transfer lines formed of vacuum-deposited metal; the polysilicon layers of the second and third levels being formed so as to pass over the polysilicon layer of the first level wherein the transfer lines are superimposed over said separations ; and connections in the form of a stairstep configuration for connecting said data transfer lines and the drain regions of said CMOS transistors said connection extending perpendicularly to said transfer lines.

Claim 10

A dynamic energy of the integrated circuit type fabricated in a silicon wafer and provided with memory cells for capacitive data storage, wherein said dynamic memory comprises: CMOS transistors fabricated in the CMOS technology for utilization as memory cells and provided with gate electrodes formed by a first level of deposited polysilicon and covered by a metallized layer to be utilized as a word line for the memory; means for capacitive storage by putting in opposition to each other, at a second and a third levels, two polysilicon layers, said second and third level polysilicon layers being separated from each other and from the first level by insulating layers of silicon oxide; regions of said second level polysilicon layer serving to form lower plates of capacitors of said cells, said regions of said second level polysilicon layer being separated by separations; data transfer lines formed of vacuum-deposited metal; the polysilicon layers of the second and third levels being formed so as to pass over the polysilicon layer of the first level wherein the transfer lines are superimposed over said separations ; and connections in the form of a stairstep configuration for connecting said data transfer lines and the drain regions of said CMOS transistors said connection extending perpendicularly to said transfer lines.