Semiconductor memory device having stacked capacitor-type memory cells

Claim 1

A semiconductor memory device comprising: a semiconductor substrate of a first conductivity type; a plurality of word lines extending in parallel over said substrate; a plurality of sense amplifiers; a plurality of pairs of bit lines extending over said substrate transversely to said word lines, each said pair of bit lines being connected to corresponding inputs of a corresponding one of said sense amplifiers, and both of the bit lines of each said pair intersecting each of said word lines; and stacked capacitor-type memory cells, each formed in the vicinity of an intersection between a corresponding one of said word lines and a corresponding one of said pairs of said bit lines, wherein each of said memory cells comprises: first and second impurity doped regions of a second conductivity type opposite to said first conductivity type formed in said substrate, each said first impurity doped region being electrically connected to a respective one of said bit lines, said first and second impurity doped regions and a respective portion of said corresponding one of said word lines forming a transfer transistor; a first conductive layer electrically connected to said second impurity doped region, for forming a first of two capacitor electrodes, said first conductive layer extending over a respective part of another one of said word lines adjacent to said corresponding word line; an insulating layer disposed on said first conductive layer; and a second conductive layer, disposed on said insulating layer, for forming the second of said two capacitor electrodes.