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US4924429A
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Hardware logic simulator
Assignee: NEC Corp
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Filing: 1988-02-24
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Granted: 1990-05-08
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Expires: 2008-02-24
Abstract
Abstract A hardware logic simulator includes a first memory, having memory locations respectively corresponding to a plurality of signals in a logic circuit to be simulated, for storing data representing states of the plurality of signals, and a second memory having memory locations respectively corresponding to those of the first memory and an address bus common therewith. When the content of a memory location at a given address of the first memory is changed during simulation, data representing the change in state of the corresponding signal is written in a second memory location corresponding to the given address. The content of the second memory is read out at the end of the simulation and the degree of completeness of the simulation is evaluated.
Inventors
- 👤 Masahiro Kurashita
- 👤 Nobuyoshi Nomizu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 06:21
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/32; G06F30/33
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
142 words
A hardware logic simulator for performing a simulator of a logic circuit including a plurality of signals, comprises: a first memory for storing first memory data at first memory locations respectively corresponding to said plurality of signals, said first memory data representing states of said plurality of signals: a second memory having second memory locations corresponding to said first memory locations and connected to said first memory through a common address bus, said second memory being arranged to store second memory data at a second memory location thereof corresponding to a given first memory location when said given first memory location is accessed during simulation, said second memory data representing state changes in said plurality of signals; and means or reading out contents at addresses of said second memory after simulation is completed and for evaluating the degree of completeness of simulation.
Claim 2
Dependent Claim
142 words
A hardware logic simulator for performing a simulator of a logic circuit including a plurality of signals, comprises: a first memory for storing first memory data at first memory locations respectively corresponding to said plurality of signals, said first memory data representing states of said plurality of signals: a second memory having second memory locations corresponding to said first memory locations and connected to said first memory through a common address bus, said second memory being arranged to store second memory data at a second memory location thereof corresponding to a given first memory location when said given first memory location is accessed during simulation, said second memory data representing state changes in said plurality of signals; and means or reading out contents at addresses of said second memory after simulation is completed and for evaluating the degree of completeness of simulation.
Claim 3
Dependent Claim
113 words
A simulator according to claim 1, wherein said hardware logic simulator further comprises: means for detecting a change in content of a first memory location at a given address of said first memory and providing an output; and writing means for writing data representing a change in state of a signal at a second memory location at an address in said second memory in response to said output from said detecting means, or for receiving a second memory output corresponding to said address and writing data representing a change in state of a signal at said address if said second memory output is data representing a change in the state of a signal.
Claim 4
Dependent Claim
45 words
A simulator according to claim 1, wherein said hardware logic simulator further comprises adder means for adding said second memory output corresponding to a given address and logic "1" and writing a sum in a memory location at a given address of said second memory.
Claim 5
Dependent Claim
116 words
A hardware logic simulator comprising: a model memory for storing a simulation model of a logic circuit including a plurality of signals; means for selecting a set of signals in said simulation model; an additional memory for receiving said set of signals as an address signal; means for executing a simulation according to said simulation model including said additional memory; means for writing predetermined data in a memory location at an address in said additional memory which is determined by a change in state of said set of signals during simulation; and evaluating means for reading out said data from said additional memory and evaluating said simulation using said data readout after said simulation is completed.
Claim 6
Dependent Claim
116 words
A hardware logic simulator comprising: a model memory for storing a simulation model of a logic circuit including a plurality of signals; means for selecting a set of signals in said simulation model; an additional memory for receiving said set of signals as an address signal; means for executing a simulation according to said simulation model including said additional memory; means for writing predetermined data in a memory location at an address in said additional memory which is determined by a change in state of said set of signals during simulation; and evaluating means for reading out said data from said additional memory and evaluating said simulation using said data readout after said simulation is completed.
Claim 7
Dependent Claim
83 words
A hardware logic simulator comprising: a model memory for storing intermediate language instructions of a simulation model which describes a logic circuit at corresponding addresses thereof; a flag memory, having addresses common with those of said model memory, for writing a flag in a memory location at an address corresponding to that of said model memory, said flag representing the fact that an intermediate language instruction has been completed; and means for reading out contents of said flag memory after simulation is completed.
Claim 8
Dependent Claim
83 words
A hardware logic simulator comprising: a model memory for storing intermediate language instructions of a simulation model which describes a logic circuit at corresponding addresses thereof; a flag memory, having addresses common with those of said model memory, for writing a flag in a memory location at an address corresponding to that of said model memory, said flag representing the fact that an intermediate language instruction has been completed; and means for reading out contents of said flag memory after simulation is completed.
Claim 9
Dependent Claim
64 words
A simulator according to claim 5, wherein said hardware logic simulator further comprises: means for inserting an instruction for setting flags representing the fact that instructions have been completed in all branch destinations of all branch instructions included in said intermediate language instructions stored in said model memory; and a memory location for storing said flag corresponding to an instruction for setting said flag.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-05-07 | 1993-11-06 | 1994-05-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-05-07 | 1997-11-06 | 1998-05-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-05-07 | 2001-11-06 | 2002-05-08 | $7700.00 | Window Closed / Lapsed |