Debugging microprocessor capable of switching between emulation and monitor without accessing stack area

Claim 2

A debugging microprocessor for moving into a debugging interrupt processing execution mode in response to an external supervisor interrupt instruction, comprising an execution controller for generating a supervisor interrupt acknowledge signal after an execution of an instruction being executed when a reception of a supervisor interrupt request has been completed, and also for generating a return instruction execution signal when a return instruction has been executed, a first program counter put in an operating condition when said microprocessor is in a user's program execution mode, a second program counter put in an operating condition when said microprocessor is in a debugging interrupt processing execution mode, a program counter controller coupled to receive said supervisor interrupt acknowledge signal and said return instruction execution signal and also coupled to said first and second program counters for controlling said first and second program counters, said program counter controller responding to the said supervisor interrupt acknowledge signal to disable said first program counter and to enable said second program counter so as to cause the content of said second program counter to be outputted as an address for a debug memory, and also responding to said return instruction execution signal to disable said second program counter and to enable said first program counter so as to cause the content of said first program counter to be outputted as an address for a user memory, and an address controller coupled to said first and second program counters so as to execute an instruction fetch cycle on the basis of an address outputted from an enabled one of said first and second program counters so that an instruction read in the instruction fetch cycle is fetched through an external bus and through an internal bus to a register and decoded so as to be executed, so that the content of the first program counter can be accessed in the course of the debugging interrupt processing operation.

Claim 3

A debugging microprocessor claimed in claim 1 wherein said address controller is coupled to an external address bus which is also coupled to said debug memory and said user memory, so that the content of said second program counter is outputted through said address controller and said external address bus to said debug memory at the time of executing said external supervisor interrupt instruction and the content of said first program counter is outputted through said address controller and said external address bus to said user memory at the time of executing said return instruction.

Claim 4

A debugging microprocessor claimed in claim 2 further including a segment and an adder coupled to receive and add the content of said segment and the content of said second program counter for generating an address for said debug memory.

Claim 5

A debugging microprocessor for moving into a debugging interrupt processing execution mode in response to an external supervisor interrupt instruction, comprising an execution controller for generating a supervisor interrupt acknowledge signal after an execution of an instruction being executed when reception of a supervisor interrupt request has been completed, and also for generating a return instruction execution signal when a return instruction has been executed, a first program counter put in an operating condition when said microprocessor is in a user's program execution mode, a second program counter put in an operating condition when said microprocessor is in a said debugging interrupt processing execution mode, a segment for generating a portion of an address of a debug memory, and an adder coupled to receive and add the content of said segment and the content of said second program counter for generating a completed address for said debug memory, a program counter controller coupled to receive said supervisor interrupt acknowledge signal and said return instruction execution signal and also coupled to said first and second program counters, said segment and said adder for controlling said first and second program counters, said segment and said adder, said program counter controller responding to said supervisor interrupt acknowledge signal to disable said first program counter and to enable said second program counter, said segment and said adder so as to cause an output of said adder to be outputted as the address for said debug memory, and also responding to said return instruction execution signal to disable said second program counter, said segment and said adder and to enable said first program counter so as to cause the content of said first program counter to be outputted as an address for a user memory, and an address controller coupled to said first and second program counters so as to execute an instruction fetch cycle on the basis of an address outputted from an enabled one of said first and second program counters so that an instruction read in said instruction fetch cycle is fetched through an external bus and through an internal bus to a register and decoded so as to be executed.

Claim 6

A debugging microprocessor for moving into a debugging interrupt processing execution mode in response to an external supervisor interrupt instruction, comprising an execution controller for generating a supervisor interrupt acknowledge signal after an execution of an instruction being executed when reception of a supervisor interrupt request has been completed, and also for generating a return instruction execution signal when a return instruction has been executed, a first program counter put in an operating condition when said microprocessor is in a user's program execution mode, a second program counter put in an operating condition when said microprocessor is in a said debugging interrupt processing execution mode, a segment for generating a portion of an address of a debug memory, and an adder coupled to receive and add the content of said segment and the content of said second program counter for generating a completed address for said debug memory, a program counter controller coupled to receive said supervisor interrupt acknowledge signal and said return instruction execution signal and also coupled to said first and second program counters, said segment and said adder for controlling said first and second program counters, said segment and said adder, said program counter controller responding to said supervisor interrupt acknowledge signal to disable said first program counter and to enable said second program counter, said segment and said adder so as to cause an output of said adder to be outputted as the address for said debug memory, and also responding to said return instruction execution signal to disable said second program counter, said segment and said adder and to enable said first program counter so as to cause the content of said first program counter to be outputted as an address for a user memory, and an address controller coupled to said first and second program counters so as to execute an instruction fetch cycle on the basis of an address outputted from an enabled one of said first and second program counters so that an instruction read in said instruction fetch cycle is fetched through an external bus and through an internal bus to a register and decoded so as to be executed.