Multi-way vectored interrupt capability

Claim 2

A computer system having a central processing unit (CPU) for generating I/O instruction signals, and a plurality of peripheral subsystems, each having a microprocessor including a program counter, a memory for storing a plurality of absolute address signals indicative of an address location of one of a plurality of interrupt routines stored in said memory, a multiway vectored interrupt apparatus for selecting said address location of said one of said plurality of interrupt routines comprising: (a) first means coupled to said CPU and said microprocessor and responsive to said I/O instruction signals for enabling said microprocessor for generating first address signals and second address signals; (b) second means coupled to said microprocessor and said memory and responsive to said first address signals for addressing a first address location in said memory for storing a first portion of a selected one of said plurality of absolute address signals for transfer to said program counter; (c) third means coupled to said CPU and said microprocessor and responsive to said I/O instruction signals for modifying said second address signals for generating base address signals for addressing an address location in said memory storing a second portion of said selected one of said plurality of absolute address signals for transfer to said program counter; (d) fourth means coupled to said memory and said Program Counter for transferring said first portion and said second portion of said selected one of said plurality of absolute address signals to said program counter; said second means being responsive to said first portion and said second portion of said selected one of said plurality of absolute address signals stored in said program counter for addressing said memory for reading out said one of said plurality of interrupt routines for use by said microprocessor.

Claim 3

The apparatus as recited in claim 1 wherein said program counter has a high order byte position for storing said first position of said selected one of said plurality of absolute address signals.

Claim 4

The apparatus as recited in claim 2 wherein said program counter has a low order byte position for storing said second portion of said selected one of said plurality of absolute address signals.

Claim 5

A computer system having a central processing unit (CPU) for generating input/output instructions including channel number signals and function code signals, and a plurality of peripheral subsystems, each having a memory for storing a plurality of absolute address signals indicative of an address location identifying one of a plurality of interrupt routines stored in said memory, each of said plurality of absolute address signals having high order byte signals and low order byte signals, a microprocessor including a program counter for storing said high order byte signals and said low order byte signals, and a multiway vectored interrupt apparatus for selecting said address location identifying said one of said plurality of interrupt routines comprising: (a) first means coupled to said central processing unit and said microprocessor and responsive to said channel signals for generating an interrupt signal, said micro-processor being responsive to said interrupt signal for generating first address signals and second address signals; (b) second means coupled to said memory and said microprocessor and responsive to said first address signals for fetching said high order byte signals from said memory for storage in a high order byte position of said program counter; (c) third means coupled to said second means, said microprocessor and said central processing unit and responsive to said second address signals for modifying said second address signals in accordance with said function code signals for generating base address signals for fetching said low order byte signals from said memory for storage in a low order byte position of said program counter; said second means being responsive to a selected one of said plurality of absolute address signals stored in said program counter for fetching a first byte of said one of said plurality of interrupt routines.

Claim 6

A computer system having a central processing unit (CPU) for generating input/output instructions including channel number signals and function code signals, and a plurality of peripheral subsystems, each having a memory for storing a plurality of absolute address signals indicative of an address location identifying one of a plurality of interrupt routines stored in said memory, each of said plurality of absolute address signals having high order byte signals and low order byte signals, a microprocessor including a program counter for storing said high order byte signals and said low order byte signals, and a multiway vectored interrupt apparatus for selecting said address location identifying said one of said plurality of interrupt routines comprising: (a) first means coupled to said central processing unit and said microprocessor and responsive to said channel signals for generating an interrupt signal, said micro-processor being responsive to said interrupt signal for generating first address signals and second address signals; (b) second means coupled to said memory and said microprocessor and responsive to said first address signals for fetching said high order byte signals from said memory for storage in a high order byte position of said program counter; (c) third means coupled to said second means, said microprocessor and said central processing unit and responsive to said second address signals for modifying said second address signals in accordance with said function code signals for generating base address signals for fetching said low order byte signals from said memory for storage in a low order byte position of said program counter; said second means being responsive to a selected one of said plurality of absolute address signals stored in said program counter for fetching a first byte of said one of said plurality of interrupt routines.

Claim 7

The apparatus as recited in claim 4 wherein said third means is a decoder.

Claim 8

The apparatus as recited in claim 3 wherein said I/O instruction signals include channel number signals and function code signals, said first means being responsive to said channel number signals for enabling said microprocessor and said third means being responsive to said function code signals for modifying said second address signals.