Abstract A circuit arrangement for evaluating a video synchronizing signal formed by line synchronizing pulses whose regular sequence between two fields is interrupted by a field synchronizing pulse and the time interval between the edges of a field synchronizing signal and the edges of a subsequent first line synchronizing pulse is characteristic of each field. In the circuit arrangement the evaluation of the video synchronizing signal is based on a field synchronizing pulse and the line synchronizing pulses subsequent thereto. This evaluation is effected by a detector, which detects the field synchronizing pulses in the video synchronizing signal. The circuit arrangement, a first logic circuit which is connected to the output of the detector and which the operation of a first counter clocked by an oscillator is controlled, two decoders connected to the counting stages of the first counter and supplying an output pulse, as long as the counter position cycles throug a predetermined counting range for each decoder, and a second logic circuit connected to the decoders. Also the video synchronizing signal is applied to this logic circuit. From their output variables it cna be recognized whether one of the two decoders and which one of the two decoders has supplied an output pulse during a pulse in the video synchronizing signal.
A circuit arrangement for evaluating a video synchronizing signal formed by line synchronizing pulses whose regular sequence is interrupted between two fields by a field synchronizing pulse and in which the time interval between the edges of a field synchronizing pulse and the edges of the subsequent line synchronizing pulse is characteristic of each field, characterized by 1.1 a detector for detecting the field synchronizing pulse in the video synchronizing signal, 1.2 a first logic circuit which is connected to the output of the detector for controlling the operation of a counter clocked by an oscillator, 1.3 two decoders (D1, D2) connected to the counting stages of the counter for supplying a output pulse, as long as the counter position cycles through a counting range which is predetermined for each decoder, 1.4 a second logic circuit connected to the decoders, to which also the video synchronizing signal is applied and from whose output variables it can be recognized whether one of the two decoders and which one of the two decoders has supplied an output pulse during a pulse in the video synchronizing signal.
Claim 2
Dependent Claim
184 words
A circuit arrangement for evaluating a video synchronizing signal formed by line synchronizing pulses whose regular sequence is interrupted between two fields by a field synchronizing pulse and in which the time interval between the edges of a field synchronizing pulse and the edges of the subsequent line synchronizing pulse is characteristic of each field, characterized by 1.1 a detector for detecting the field synchronizing pulse in the video synchronizing signal, 1.2 a first logic circuit which is connected to the output of the detector for controlling the operation of a counter clocked by an oscillator, 1.3 two decoders (D1, D2) connected to the counting stages of the counter for supplying a output pulse, as long as the counter position cycles through a counting range which is predetermined for each decoder, 1.4 a second logic circuit connected to the decoders, to which also the video synchronizing signal is applied and from whose output variables it can be recognized whether one of the two decoders and which one of the two decoders has supplied an output pulse during a pulse in the video synchronizing signal.
Claim 3
Dependent Claim
95 words
A circuit arrangement as claimed in claim 1, characterized, in that the first logic circuit is constituted by a gate, which supplies a pulse in the presence of a pulse at the output of the detector or when predetermined binary values are stored in selected counting stages of the counter, the counter being operative during this pulse, whereby in contrast whereto, in the absence of such a pulse, the counter is loaded with a number which results in the storage of binary values other than the predetermined binary values stored in the selected counting stages.
Claim 4
Dependent Claim
57 words
A circuit arrangement as claimed in claim 1 or 2, characterized, in that the second logic circuit is formed by two AND-gates each having two inputs, that each time one input of the AND-gate receives the video synchronizing signal and the other input of each one of the AND-gates is connected to the output of a decoder.