US4459612A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Vertical synchronizing signal detecting circuit
Assignee: Sony Corp
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Filing: 1982-09-14
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Granted: 1984-07-10
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Expires: 2002-09-14
Abstract
Abstract Digitally designed vertical synchronizing separator and framing circuit in association with a digital servo LSI for a video tape recorder are particularly designed to be noise-free system for a composite synchronizing signal reproduced from the video tape recorder and utilize a reference clock pulse with the synchronizing signal and a counter with a feed back of the contents of the counter to control the supply of said composite synchronizing signal.
Inventors
- 👤 Mitsutoshi Shinkai
- 👤 Masaaki Sakai
- 👤 Kenji Nakano
- 👤 Tadahiko Nakamura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 17:41
CPC Classifications
H; H04; H04N; H04N5/00; H04N5/04; H04N5/08; H04N5/10; G; G11; G11B; G11B15/00; G11B15/60; G11B15/602; G11B27/00; G11B27/02; G11B27/022; G11B27/024
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
126 words
A circuit for generating a vertical synchronizing pulse comprising, a first flip-flop circuit which receives an incoming composite sync signal including horizontal and vertical sync signals and equilizing pulses, a first multibit counter, a first AND gate receiving the output of said first flip-flop circuit and an incoming clock signal and supplying an input to said first multibit counter, a logic circuit receiving multiple outputs of said multibit counter and producing a window signal, a second multibut counter, a second AND gate receiving the output of said logic circuit and said incoming composite sync signal and supplying a reset pulse to said first and second multibit counters, and said second multibit counter receiving an input from said first multibit counter and producing said vertical sync pulse.
Claim 2
Dependent Claim
126 words
A circuit for generating a vertical synchronizing pulse comprising, a first flip-flop circuit which receives an incoming composite sync signal including horizontal and vertical sync signals and equilizing pulses, a first multibit counter, a first AND gate receiving the output of said first flip-flop circuit and an incoming clock signal and supplying an input to said first multibit counter, a logic circuit receiving multiple outputs of said multibit counter and producing a window signal, a second multibut counter, a second AND gate receiving the output of said logic circuit and said incoming composite sync signal and supplying a reset pulse to said first and second multibit counters, and said second multibit counter receiving an input from said first multibit counter and producing said vertical sync pulse.
Claim 3
Dependent Claim
19 words
A circuit according to claim 1 wherein said logic circuit includes a third AND gate and an OR gate.
Claim 4
Dependent Claim
17 words
A circuit according to claim 2 wherein said logic circuit also includes first, second and third inverters.
Claim 5
Dependent Claim
16 words
A circuit according to claim 1 wherein said second multibit counter is a four bit counter.
Claim 6
Dependent Claim
159 words
A circuit according to claim 1 for generating a framing signal comprising a second flip-flop receiving said vertical sync pulse from said second multibit counter and with a first output comprising said framing signal, a first differential circuit receiving said incoming composite sync signal, a third flip-flop receiving the output of said first differential circuit, third and fourth counters receiving incoming clock signals, a fourth AND gate receiving inputs from said first differential circuit and said third flip-flop and supplying a reset signal to said third counter, a decoder receiving the output of said third counter and supplying outputs to said fourth counter and to said third flip-flop, a fifth AND gate receiving the output of said fourth counter and said vertical sync pulse, a second differential circuit receiving the output of said fifth AND gate, and a noise inhibiting circuit connected to the output of said second differential circuit and supplying a reset signal to said second flip-flop.
Claim 7
Dependent Claim
82 words
A circuit according to claim 5 wherein said noise inhibiting circuit comprises sixth and seventh AND gates which receive inputs from said second flip-flop and said second differential circuit, a fifth counter connected to receive the output of said sixth AND gate, a second decoder connected to the output of said fifth counter, and a second OR gate connected to receive the outputs of said seventh AND gate and said second decoder and to supply an output to reset said second flip-flop.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-07-10 | 1988-01-09 | 1988-07-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-07-10 | 1992-01-09 | 1992-07-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-07-10 | 1996-01-09 | 1996-07-10 | $7700.00 | Window Closed / Lapsed |