Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
213 words
A vertical synchronizing signal detector circuit comprising: (a) an input terminal for receiving a composite synchronizing signal including a horizontal synchronizing signal and vertical synchronizing signal, (b) an output terminal for providing a vertical synchronizing pulse synchronized with the vertical synchronizing signal, (c) a clock pulse generator circuit connected to said input terminal and adapted to generate a clock pulse having half the period of the horizontal synchronizing signal and a phase lag therefrom of one-fourth the period thereof, (d) a vertical synchronizing signal extractor circuit connected to said input terminal and said clock pulse generator circuit and adapted to compare the vertical synchronizing signal with a reference waveform pattern of the vertical synchronizing signal so as to generate a vertical synchronizing signal output synchronized with the vertical synchronizing signal only when the comparison results in a complete coincidence, and (e) a vertical synchronizing signal compensator circuit connected to said vertical synchronizing signal extractor circuit and said clock pulse generator circuit and responsive to the vertical synchronizing signal output to provide this output at said output terminal and simultaneously store the same temporarily, said vertical synchronizing signal compensator circuit being also adapted to provide the stored vertical synchronizing signal output at said output terminal when the vertical synchronizing signal output is not received.
Claim 2
Dependent Claim
213 words
A vertical synchronizing signal detector circuit comprising: (a) an input terminal for receiving a composite synchronizing signal including a horizontal synchronizing signal and vertical synchronizing signal, (b) an output terminal for providing a vertical synchronizing pulse synchronized with the vertical synchronizing signal, (c) a clock pulse generator circuit connected to said input terminal and adapted to generate a clock pulse having half the period of the horizontal synchronizing signal and a phase lag therefrom of one-fourth the period thereof, (d) a vertical synchronizing signal extractor circuit connected to said input terminal and said clock pulse generator circuit and adapted to compare the vertical synchronizing signal with a reference waveform pattern of the vertical synchronizing signal so as to generate a vertical synchronizing signal output synchronized with the vertical synchronizing signal only when the comparison results in a complete coincidence, and (e) a vertical synchronizing signal compensator circuit connected to said vertical synchronizing signal extractor circuit and said clock pulse generator circuit and responsive to the vertical synchronizing signal output to provide this output at said output terminal and simultaneously store the same temporarily, said vertical synchronizing signal compensator circuit being also adapted to provide the stored vertical synchronizing signal output at said output terminal when the vertical synchronizing signal output is not received.
Claim 3
Dependent Claim
83 words
A vertical synchronizing signal detector circuit according to claim 1, wherein said vertical synchronizing signal extractor circuit comprises a 17-stage shift register connected to said input terminal and said clock pulse generator circuit, six inverters, and an AND gate for receiving the outputs from the 7th to 12th stages of said shift register through said respective inverters and simultaneously receiving the outputs from the other eleven stages directly so as to produce the logical product of all said outputs from said shift register.
Claim 4
Dependent Claim
201 words
A vertical synchronizing signal detector circuit according to claim 1 or 2, wherein said vertical synchronizing signal compensator circuit comprises a single-stage shift register connected to said vertical synchronizing signal extractor circuit and said clock pulse generator circuit and adapted to shift the vertical synchronizing signal output by one period of the clock pulse, a flip-flop adapted to be set by the output from said single-stage shift register, a first AND gate responsive to the set output from said flip-flop to produce a clock pulse, a 524-scale counter, cleared by the output of said single-stage shift register, for counting the output from said first AND gate, a second AND gate adapted to operate in response to the reset output from said flip-flop when said flip-flop is reset by the output of said counter, a first OR gate for producing at said output terminal the logical sum of the output of said second AND gate and the vertical synchronizing signal output, and a 525-stage shift register for receiving the output of said first OR gate and said clock pulse and for supplying the output of said first OR gate to said second AND gate at the time of having received 525 pulses.
Claim 5
Dependent Claim
104 words
A vertical synchronizing signal detector circuit according to claim 1 or 2, wherein said vertical synchronizing signal compensator circuit comprises a multivibrator to the vertical synchronizing signal output to produce a trigger pulse, a 525-stage shift register for shifting the vertical synchronizing signal output in accordance with said clock pulse so as to produce an output at the time of having receiving 525 of said clock pulse, said 525-stage shift register being cleared by said trigger pulse, and a second OR gate for producing at said output terminal the logical sum of the output of said 525-stage shift register and the vertical synchronizing signal.
Claim 6
Dependent Claim
29 words
A vertical synchronizing signal detector circuit according to claim 1 or 2, wherein said reference waveform pattern for the vertical synchronizing signal in accordance with NTSC system is "11111100000011111".
Claim 7
Dependent Claim
31 words
A vertical synchronizing signal detector circuit according to claim 1 or 2, wherein said reference waveform pattern for the vertical synchronizing signal in accordance with PAL and SECAM systems is "1111110000011111".