Apparatus and process for the simultaneous continuity sensing of multiple circuits

Claim 1

A process for simultaneously testing a plurality of electrical circuits in a circuit configuration to detect an error condition with respect to one or more of the electrical test circuits, including the steps of: providing a plurality of electrical test circuits, each having a test circuit input and a test circuit output; and providing a plurality of comparator means, one associated with each test circuit, each comparator means including first and second comparator inputs; biasing each of said test circuit inputs and its associated one of said first comparator input to a first voltage level; generating a second voltage level corresponding to the voltage level at said test circuit output and less than said first voltage level, and providing said second voltage level to the associated one of said second comparator inputs; connecting each of said test circuit outputs and associated second comparator inputs to a low voltage terminal through a sensor resistor having a resistance substantially greater than a nominal resistance of its associated test circuit, and biasing said low voltage terminals to a third voltage level less than said second voltage; generating a comparator output for each comparator comprising a first logic state whenever the voltage at the first comparator input exceeds the voltage at the second comparator input by a prerdetermined thershold level, and further comprising a second logic state whenever the voltage at the first comparator input does not exceed the voltage at the second comparator input by at least the predetermined threshold; and simultaneously sensing the logic state outputs of the comparator means.

Claim 4

An apparatus for simultaneously testing a plurality of electrical circuits in a circuit configuration to depict an error condition with respect to one or more of the tested circuits, said apparatus including: a plurality of sensing circuits, each sensing circuit associated with one of a plurality of test circuits with each test circuit including a test circuit input and a test circuit output; each sensing circuit comprising: a comparator means having first and second comparator inputs and a predetermined threshold voltage between said first comparator input and said second comparator input; an input voltage means for providing a first voltage level to said first comparator input and to the test circuit input of the associated test circuit; an output voltage means connected to the test circuit output of the associated test circuit and to the second comparator input for providing a second voltage level to said second comparator input, less than said first voltage and corresponding to the voltage at the test circuit output; and a low voltage terminal and a sensor output resistor connected to the low voltage terminal and to said output voltage means, said sensing resistor having a resistance substantially greater than a nominal resistance of the associated test circuit; wherein each of said comparator means generates a comparator output comprising first and second alternative logic states, said first state being generated whenever said first voltage exceeds the second voltage by at least said predetermined threshold and said second state being generated whenever said first voltage does not exceed the second voltage by at least the predetermined threshold; and wherein one of said first and second logic states indicates a normal condition with respect to the associated test circuit, the other of said states indicating an error condition with respect to the associated test circuit; a digital sensing means for simultaneously sensing the comparator outputs of said comparator means as a digital word representing the conditions of the test circuits, and a control means for generating a storage command signal responsive to the sensing of an error condition at any of said comparator outputs; and a storage means including a plurality of channels, one channel associated with each of said sensing circuits, for storing the comparator outputs of said comparator means responsive to receiving said storage command signal.

Claim 5

An apparatus for simultaneously testing a plurality of electrical circuits in a circuit configuration to depict an error condition with respect to one or more of the tested circuits, said apparatus including: a plurality of sensing circuits, each sensing circuit associated with one of a plurality of test circuits with each test circuit including a test circuit input and a test circuit output; each sensing circuit comprising: a comparator means having first and second comparator inputs and a predetermined threshold voltage between said first comparator input and said second comparator input; an input voltage means for providing a first voltage level to said first comparator input and to the test circuit input of the associated test circuit; an output voltage means connected to the test circuit output of the associated test circuit and to the second comparator input for providing a second voltage level to said second comparator input, less than said first voltage and corresponding to the voltage at the test circuit output; and a low voltage terminal and a sensor output resistor connected to the low voltage terminal and to said output voltage means, said sensing resistor having a resistance substantially greater than a nominal resistance of the associated test circuit; wherein each of said comparator means generates a comparator output comprising first and second alternative logic states, said first state being generated whenever said first voltage exceeds the second voltage by at least said predetermined threshold and said second state being generated whenever said first voltage does not exceed the second voltage by at least the predetermined threshold; and wherein one of said first and second logic states indicates a normal condition with respect to the associated test circuit, the other of said states indicating an error condition with respect to the associated test circuit; a digital sensing means for simultaneously sensing the comparator outputs of said comparator means as a digital word representing the conditions of the test circuits, and a control means for generating a storage command signal responsive to the sensing of an error condition at any of said comparator outputs; and a storage means including a plurality of channels, one channel associated with each of said sensing circuits, for storing the comparator outputs of said comparator means responsive to receiving said storage command signal.