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Patent US4921810A successfully refreshed from Google Patents.
US4921810A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for testing semiconductor devices
Assignee: NEC Electronics America Inc
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Filing: 1988-06-22
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Granted: 1990-05-01
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Expires: 2008-06-22
Abstract
Abstract A method for electrically testing integrated circuits in a wafer comprises the steps of forming a layer of material (20) on the surface of the wafer having a dielectric constant which simulates the dielectric constant of the packaging material which will eventually encapsulate the integrated circuits. In one embodiment, photoresist is formed on the integrated circuit prior to wafer test. In this way, during wafer test, the capacitive coupling between the conductive structures (14) in the integrated circuit will accurately simulate the capacitive coupling between these structures after the integrated circuit is encapsulated in the packaging material.
Inventors
- 👤 Shin-ichi Kunieda
- 👤 Masahide Ozawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 07:14
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/282; G01R31/2831; G01R31/316; H; H10; H10W; H10W72/00; H10W72/90; H10W72/981; H10W72/983; H10W74/00
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
64 words
A method for testing an integrated circuit comprising the steps of: applying a layer of material to a surface of said integrated circuit, said layer of material having a dielectric constant greater than 1; electrically testing said integrated circuit, the electrical test including effects of capacitive coupling; removing said layer of material from said surface of said integrated circuit; and packaging said integrated circuit.
Claim 2
Independent Claim
64 words
A method for testing an integrated circuit comprising the steps of: applying a layer of material to a surface of said integrated circuit, said layer of material having a dielectric constant greater than 1; electrically testing said integrated circuit, the electrical test including effects of capacitive coupling; removing said layer of material from said surface of said integrated circuit; and packaging said integrated circuit.
Claim 3
Dependent Claim
12 words
The method of claim 1 wherein said layer of material comprises photoresist.
Claim 4
Dependent Claim
17 words
The method of claim 1 wherein said layer of material has a dielectric constant greater than 2.
Claim 5
Dependent Claim
17 words
The method of claim 1 wherein said layer of material has a dielectric constant of about 6.
Claim 6
Dependent Claim
47 words
The method of claim 1 wherein said integrated circuit includes an insulating layer formed thereon, said insulating layer comprising at least one of the materials within the class of materials consisting of silicon dioxide and silicon nitride, said layer of material being formed on said insulating layer.
Claim 7
Dependent Claim
17 words
The method of claim 1 wherein said layer of material is greater than about 1 micron thick.
Claim 8
Independent Claim
74 words
A method for testing integrated circuits in a wafer comprising the steps of: applying a layer of material to a surface of said wafer, said layer of material having a dielectric constant greater than 1; electrically testing the integrated circuit within said wafer, the electrical test including effects of capacitive coupling; removing said layer of material from said surface of said wafer; cutting said wafer into individual integrated circuits; and packaging said integrated circuits.
Claim 9
Independent Claim
74 words
A method for testing integrated circuits in a wafer comprising the steps of: applying a layer of material to a surface of said wafer, said layer of material having a dielectric constant greater than 1; electrically testing the integrated circuit within said wafer, the electrical test including effects of capacitive coupling; removing said layer of material from said surface of said wafer; cutting said wafer into individual integrated circuits; and packaging said integrated circuits.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-04-30 | 1993-10-30 | 1994-05-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-04-30 | 1997-10-30 | 1998-05-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-04-30 | 2001-10-30 | 2002-05-01 | $7700.00 | Window Closed / Lapsed |