Patent US4920544A successfully refreshed from Google Patents.
US4920544A
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Delta-sigma modulator
Assignee: Denso Ten Ltd
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Filing: 1989-02-10
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Granted: 1990-04-24
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Expires: 2009-02-10
Abstract
Abstract The delta-sigma modulator includes a secondary delta-sigma modulator which carries out a secondary delta-sigma modulation for an analog input signal, thereby producing a first quantization signal. A quantization noise extractor extracts a quantization noise occurring in the secondary delta-sigma modulator. A primary delta-sigma modulator carries out a first delta-sigma modulator for the quantization noise, thereby producing a second quantization signal. A differentiating circuit differentiates the second quantization signal supplied from the primary delta-sigma modulator. An adder adds the first quantization signal and an output signal of the differentiating circuit, thereby producing a digital output signal corresponding to the analog input signal.
Inventors
- 👤 Seiji Endo
- 👤 Osamu Kobayashi
- 👤 Masatsugu Kamimura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 13:39
CPC Classifications
H; H03; H03M; H03M3/00; H03M3/02; H04; H04B; H04B14/00; H04B14/02; H04B14/04; H04B14/046; H03M3/30; H03M3/39; H03M3/412; H03M3/414; H03M3/418
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
107 words
A delta-sigma modulator comprising: secondary delta-sigma modulation means for carrying out a secondary delta-sigma modulation for an analog input signal, thereby producing a first quantization signal; quantization noise extracting means for extracting a quantization noise occurring in said secondary delta-sigma modulation means; primary delta-sigma modulation means for carrying out a first delta-sigma modulation for said quantization noise, thereby producing a second quantization signal; differentiating means for differentiating said second quantization signal supplied from said primary delta-sigma modulation means; and adding means for adding said first quantization signal and an output signal of said differentiating means, thereby producing a digital output signal corresponding to said analog input signal.
Claim 2
Dependent Claim
107 words
A delta-sigma modulator comprising: secondary delta-sigma modulation means for carrying out a secondary delta-sigma modulation for an analog input signal, thereby producing a first quantization signal; quantization noise extracting means for extracting a quantization noise occurring in said secondary delta-sigma modulation means; primary delta-sigma modulation means for carrying out a first delta-sigma modulation for said quantization noise, thereby producing a second quantization signal; differentiating means for differentiating said second quantization signal supplied from said primary delta-sigma modulation means; and adding means for adding said first quantization signal and an output signal of said differentiating means, thereby producing a digital output signal corresponding to said analog input signal.
Claim 3
Dependent Claim
52 words
A delta-sigma modulator as claimed in claim 1, wherein the secondary delta-sigma modulation means comprises first- and second-stage integral circuits cascaded, and a first quantizer having an input terminal connected to said second-stage integral circuit and said quantization noise extracting means, and an output terminal connected to said quantization noise extracting means.
Claim 4
Dependent Claim
45 words
A delta-sigma modulator as claimed in claim 2, wherein said quantization noise extracting means comprises a subtracter having a first input terminal connected to the input terminal of said first quantizer, and a second input terminal connected to the output terminal of said first quantizer.
Claim 5
Dependent Claim
21 words
A delta-sigma modulator as claimed in claim 1, wherein said differentiating means comprises first and second differentiating portions which are cascaded.
Claim 6
Dependent Claim
42 words
A delta-sigma modulator as claimed in claim 1, further comprising delay means for delaying said first quantization signal by a predetermined time so as to fit, on the time axis, said first quantization signal into the output signal of said differentiating means.
Claim 7
Dependent Claim
47 words
A delta-sigma modulator as claimed in claim 2, wherein said secondary delta-sigma modulation means comprises corresponding switched capacitor means, and said delta-sigma modulator further comprises switch control means for generating switch control signals to be supplied to said switched capacitor means by using said first quantization signal.
Claim 8
Dependent Claim
46 words
A delta-sigma modulator as claimed in claim 1, wherein said primary delta-sigma modulator means comprises switched capacitor means, and said delta-sigma modulator further comprises switch control means for generating switch control signals to be supplied to said switched capacitor means by using said second quantization signal.
Claim 9
Dependent Claim
51 words
A delta-sigma modulator as claimed in claim 1, said first quantization signal derived from said secondary delta-sigma modulation means has the following transfer characteristic: F=Ain+(1-z.sup.-1).sup.2 Q1 where F is said first quantization signal, Ain is said analog input signal, Q1 denotes said quantization noise, and z -1 denotes a unit delay.
Claim 10
Dependent Claim
43 words
A delta-sigma modulator as claimed in claim 8, wherein said second quantization signal derived from said primary delta-sigma modulator has the following transfer characteristic: J=-Q1+(1-z.sup.-1)Q2 where J is the second quantization signal, Q2 is a quantization noise occurring in said primary delta-sigma modulator.
Claim 11
Dependent Claim
22 words
A delta-sigma modulator as claimed in claim 9, wherein the output signal of said differentiating means has the following transfer characteristic: ##EQU3##
Claim 12
Dependent Claim
25 words
A delta-sigma modulator as claimed in claim 10, wherein the digital output signal derived from said adding means has the following transfer characteristic: J'+F=Ain+(1+z.sup.-1).sup.3 Q2.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-04-23 | 1993-10-23 | 1994-04-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-04-23 | 1997-10-23 | 1998-04-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-04-23 | 2001-10-23 | 2002-04-24 | $7700.00 | Window Closed / Lapsed |