Delta-Sigma modulator with switch capacitor implementation

Claim 2

A delta-sigma modulator for digitally encoding an analog signal, comprising: means for generating a timing waveform having a frequency substantially higher than the highest frequency component of said analog signal; sampling means including switching capacitance means for storing charge representative of instantaneous amplitude values of said analog signal said values being determined by the ratios of the values of a plurality of said capacitance means, and having an output; lowpass filter means for performing an integration function on the output of said sampling means; one-bit analog-to-digital converter means clocked by said timing waveform and providing first and second outputs in response to the instantaneous polarity of the output of said lowpass filter means, said second output being complementary of said first output; reference means for selectively applying a charging voltage to said lowpass filter such that said capacitance means charges and discharges in non-overlapping intervals of time.

Claim 3

A modulator according to claim 1 wherein said one-bit analog-to-digital converter includes a comparator having a stabilized input voltage during the interval when a comparison of voltages is made.

Claim 4

A Delta-Sigma ΔΣ modulator for digitally encoding an analog input signal, comprising: clock means for generating a recurring timing gate waveform having first and second levels and first and second switching gates within the duration of but not overlapping said timing gate first and second levels, respectively, said timing gate and said switching gates having a frequency high compared to the highest frequency component of said analog signal; a first sampling circuit including switching means and a first capacitor for storing the instantaneous amplitude value of said analog input signal during said first switching gate and for outputting said stored amplitude value during said second switching gate; first integrating means operative as a first low-pass filter responsive to the output of said first means; a second sampling circuit including a second capacitor and switching means for storing the instantaneous amplitude value of the output signal of said first integrating means during said first switching gate and for outputting said stored amplitude value during said second switching gate; second integrating means operative as a second low-pass filter responsive to the output of said second sampling circuit; a one-bit analog-to-digital converter clocked by said timing gate waveform and providing Q and Q outputs as a function of the corresponding instantaneous polarity of the output signal of said second integrating means; reference means including a third capacitor and additional switching means connected to charge said third capacitor to +V or -V reference voltage during said first switching gate in polarity corresponding to θnQ or θ 1 nQ, respectively, where θ 1 is said first switching gate and θ 2 is said second switching gate and to apply said third capacitor voltage to said first integrating means input during said θ 2 time; and second reference means including a fourth capacitor and second additional switching means connected to charge said fourth capacitor to +V or -V reference voltage during said first switching signal in polarity corresponding to θ 1 nQ or θ 1 nQ, respectively, and to apply said fourth capacitor voltage to said second integrating means input during said θ 2 time.

Claim 5

A Delta-Sigma ΔΣ modulator for digitally encoding an analog input signal, comprising: clock means for generating a recurring timing gate waveform having first and second levels and first and second switching gates within the duration of but not overlapping said timing gate first and second levels, respectively, said timing gate and said switching gates having a frequency high compared to the highest frequency component of said analog signal; a first sampling circuit including switching means and a first capacitor for storing the instantaneous amplitude value of said analog input signal during said first switching gate and for outputting said stored amplitude value during said second switching gate; first integrating means operative as a first low-pass filter responsive to the output of said first means; a second sampling circuit including a second capacitor and switching means for storing the instantaneous amplitude value of the output signal of said first integrating means during said first switching gate and for outputting said stored amplitude value during said second switching gate; second integrating means operative as a second low-pass filter responsive to the output of said second sampling circuit; a one-bit analog-to-digital converter clocked by said timing gate waveform and providing Q and Q outputs as a function of the corresponding instantaneous polarity of the output signal of said second integrating means; reference means including a third capacitor and additional switching means connected to charge said third capacitor to +V or -V reference voltage during said first switching gate in polarity corresponding to θnQ or θ 1 nQ, respectively, where θ 1 is said first switching gate and θ 2 is said second switching gate and to apply said third capacitor voltage to said first integrating means input during said θ 2 time; and second reference means including a fourth capacitor and second additional switching means connected to charge said fourth capacitor to +V or -V reference voltage during said first switching signal in polarity corresponding to θ 1 nQ or θ 1 nQ, respectively, and to apply said fourth capacitor voltage to said second integrating means input during said θ 2 time.

Claim 6

The modulator according to claim 3 in which said first and second integrators comprise corresponding inverting first and second operational amplifiers having fifth and sixth capacitors, connected between input and output of said first and second amplifiers, respectively.

Claim 7

The modulator according to claim 4 in which the ratio of the capacitance of said first capacitor to that of said third capacitor, and the capacitance ratio of said third capacitor to that of said fifth capacitor is approximately 1/2; the ratio of the capacitance of said second capacitor to that of said sixth capacitor and the capacitance ratio of said fourth capacitor to that of said sixth capacitor being unity.

Claim 8

The modulator according to claim 4 wherein the ratio of capacitances is selectively variable.

Claim 9

The modulator according to claim 5 in which said first reference means includes additional switch means associated with said third capacitor for switching the terminal of said third capacitor which is connected to ground potential to the positive terminal thereof during the time of θ 2 nQ and to the negative terminal thereof during θ 1 , said third capacitor voltage being outputted to said first integrating means during θ 2 nQ, said second reference means comprising second additional switch means associated with said fourth capacitor for switching the terminal thereof which is connected to ground potential to the positive terminal thereof during the time θ 2 nQ and to the negative terminal during θ 1 , said fourth capacitor voltage being outputted to said second integrating means during θ 2 nQ, thereby to provide the function of said reference means using only a positive reference voltage.

Claim 10

The modulator according to claim 3 in which said first reference means includes additional switch means associated with said third capacitor for switching the terminal of said third capacitor which is connected to ground potential to the positive terminal thererof during the time of θ 2 nQ and to the negative terminal thereof during θ 1 , said third capacitor voltage being outputted to said first integrating means during θ 2 nQ, said second reference means comprising second additional switch means associated with said fourth capacitor for switching the terminal thereof which is connected to ground potential to the positive terminal thereof during the time θ 2 nQ and to the negative terminal during θ 1 , said fourth capacitor voltage being outputted to said second integrating means during θ 2 nQ, thereby to provide the function of said reference means using only a positive reference voltage.

Claim 11

The modulator according to claim 8 in which said one-bit analog-to-digital converter comprises a comparator responding to said second integrator to provide a polarity responsive output having a first or second condition, and a D type flip flop circuit responsive to said comparator output for providing Q and Q outputs, said Q output providing the one-bit code.

Claim 12

The modulator according to claim 8 in which said switching means comprise individual signal controlled electronic switches.

Claim 13

The modulator according to claim 3 in which said one-bit analog-to-digital converter comprises a comparator responding to said second integrator to provide a polarity responsive output having a first or second condition, and a D type flip-flop circuit responsive to said comparator output for providing Q and Q outputs, said Q output providing the one-bit code.

Claim 14

The modulator according to claim 3 in which said clock means is further defined as generating said switching gates each substantially time-centered within the duration of the corresponding timing gate.

Claim 15

The modulator according to claim 3 in which said switching means comprise individual signal controlled electronic switches.