Patent US4920073A successfully refreshed from Google Patents.
US4920073A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Selective silicidation process using a titanium nitride protective layer
Assignee: Texas Instruments Inc
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Filing: 1989-05-11
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Granted: 1990-04-24
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Expires: 2009-05-11
Abstract
Abstract The present invention provides a method for inhibiting the oxidation of a titanium layer during the direct reaction of the titanium with exposed silicon areas of an integrated circuit. In one embodiment of the present invention, a titanium nitride layer is formed on the surface of the titanium layer in the reactor where the titanium layer is deposited. The titanium nitride layer provides an effective barrier against oxidation. Thus, the formation of titanium dioxide is inhibited. In addition, in those areas where titanium nitride local interconnect is to be formed between diffused areas, the extra thickness provided by the top titanium nitride layer adds in the integrity of the conductive layers. By conducting the silicidation in a nitride atmosphere, diffusion of the nitride from the titanium nitride layer into the titanium layer and substitution of those lost nitrogen atoms by the atmosphere occurs thus providing a blocking layer for the formation of titanium silicide shorts.
Inventors
- 👤 Che-Chia Wei
- 👤 Thomas E. Tang
- 👤 James G. Bohlman
- 👤 Monte A. Douglas
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 05:49
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0212; H10P; H10P14/00; H10P14/60; H10P14/63; H10P14/6302; H10P14/6316; Y; Y10; Y10S; Y10S148/00; Y10S148/113; Y10S148/147
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
113 words
A method for forming high conductivity regions in selected regions of a silicon integrated circuit, comprising the steps of: depositing a layer of titanium overall said silicon integrated circuit; depositing a layer of titanium nitride on said layer of titanium; heating said integrated circuit to a temperature sufficient to cause said layer of titanium to react with said selected regions of said silicon integrated circuit to form titanium silicide; patterning and etching said layer of titanium nitride to provide conductive titanium nitride connection between elements of said integrated circuit said etching removing said layer of titanium nitride from above said titanium silicide where said silicide is not in contact with said conductive connection;
Claim 2
Independent Claim
113 words
A method for forming high conductivity regions in selected regions of a silicon integrated circuit, comprising the steps of: depositing a layer of titanium overall said silicon integrated circuit; depositing a layer of titanium nitride on said layer of titanium; heating said integrated circuit to a temperature sufficient to cause said layer of titanium to react with said selected regions of said silicon integrated circuit to form titanium silicide; patterning and etching said layer of titanium nitride to provide conductive titanium nitride connection between elements of said integrated circuit said etching removing said layer of titanium nitride from above said titanium silicide where said silicide is not in contact with said conductive connection;
Claim 3
Dependent Claim
12 words
The method of claim 1 wherein said selected regions comprise crystalline silicon.
Claim 4
Dependent Claim
12 words
The method of claim 1 wherein said selected regions comprise polycrystalline silicon.
Claim 5
Dependent Claim
46 words
A method as in claim 1 wherein said selected regions comprises a layer of polycrystalline silicon separated from the substrate of said integrated circuit by an insulating layer, further comprising the step of forming sidewall oxide layers on the sides of said layer of polycrystalline silicon.
Claim 6
Independent Claim
135 words
A method for forming high conductivity regions in selected regions of a silicon integrated circuit, comprising the steps of: placing said silicon integrated circuit in a controlled environment chamber and depositing a layer of titanium overall said silicon integrated circuit; depositing a layer of titanium nitride on said layer of titanium in said chamber without removing said integrated circuit from said chamber; heating said integrated circuit to a temperature sufficient to cause said layer of titanium to react with said selected regions of said silicon integrated circuit to form titanium silicide; patterning and etching said layer of titanium nitride to provide conductive titanium nitride connection between elements of said silicon integrated, said etching removing said layer of titanium nitride from above said titanium silicide where said silicide is not in contact with said conductive connection.
Claim 7
Independent Claim
135 words
A method for forming high conductivity regions in selected regions of a silicon integrated circuit, comprising the steps of: placing said silicon integrated circuit in a controlled environment chamber and depositing a layer of titanium overall said silicon integrated circuit; depositing a layer of titanium nitride on said layer of titanium in said chamber without removing said integrated circuit from said chamber; heating said integrated circuit to a temperature sufficient to cause said layer of titanium to react with said selected regions of said silicon integrated circuit to form titanium silicide; patterning and etching said layer of titanium nitride to provide conductive titanium nitride connection between elements of said silicon integrated, said etching removing said layer of titanium nitride from above said titanium silicide where said silicide is not in contact with said conductive connection.
Claim 8
Dependent Claim
12 words
The method of claim 5 wherein said selected regions comprise crystalline silicon.
Claim 9
Dependent Claim
12 words
The method of claim 5 wherein said selected regions comprise polycrystalline silicon.
Claim 10
Dependent Claim
46 words
A method as in claim 5 wherein said selected regions comprise a layer of polycrystalline silicon separated from the substrate of said integrated circuit by an insulating layer, further comrising the step of forming sidewall oxide layers on the sides of said layer of polycrystalline silicon.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-04-23 | 1993-10-23 | 1994-04-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-04-23 | 1997-10-23 | 1998-04-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-04-23 | 2001-10-23 | 2002-04-24 | $7700.00 | Window Closed / Lapsed |