US4920062A
Expired / Lapsed
US
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Manufacturing method for vertically conductive semiconductor devices
Assignee: Toshiba Corp
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Filing: 1989-05-16
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Granted: 1990-04-24
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Expires: 2009-05-16
Abstract
Abstract A first semiconductor layer is formed on a semiconductor anode layer containing a high concentration of impurity of a first conductivity type. This first semiconductor layer contains an impurity in a lower concentration than the impurity concentration of the anode layer on which it is formed. A second semiconductor layer containing a high concentration of impurity of a second conductive type is formed on the first semiconductor layer, and a third semiconductor layer containing a low concentration of impurity of the second conductive type is formed on the second semiconductor layer. Impurity regions of at least the first conductivity type are formed by thermal diffusion in the surface region of this third semiconductor layer. During the thermal diffusion, the impurity contained in the anode layer diffuses into the first semiconductor layer. However, the concentration and thickness of the first semiconductor layer are specified so that, even after thermal diffusion, the concentration of the second semiconductor layer is not essentially changed, and thus a semiconductor device which has a thin, high concentration buffer layer can be provided by this production method.
Inventors
- 👤 Tetsujiro Tsunoda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 05:58
CPC Classifications
H; H10; H10D; H10D12/00; H10D12/01; H10D12/021; H10D12/031; H10D12/032; H10D62/00; H10D62/10; H10D62/13; H10D62/141; H10D62/142; Y; Y10; Y10S; Y10S148/00; Y10S148/126
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
166 words
A method for manufacturing a vertical conducting power semiconductor device having cathode, anode and gate electrode, comprising the steps of: preparing a highly doped semiconductor substrate of a first conductivity type; forming a first semiconductor layer on said semiconductor substrate which has a lower impurity concentration than that of said semiconductor substrate; forming a highly doped second semiconductor layer of a second conductivity type in said first semiconductor layer; forming a lightly doped third semiconductor layer of said second conductivity type on said second semiconductor layer; forming a first impurity doped region of said first conductivity type in said third semiconductor layer which is diffused from a surface of said third semiconductor layer by a heating process; and diffusing impurities of first conductivity type of said semiconductor substrate into said first semiconductor layer when said impurity doped region is diffused by said heating process, so as to maintain the impurity concentration of said second semiconductor layer at a constant level and substantially maintain the same thickness.
Claim 2
Independent Claim
166 words
A method for manufacturing a vertical conducting power semiconductor device having cathode, anode and gate electrode, comprising the steps of: preparing a highly doped semiconductor substrate of a first conductivity type; forming a first semiconductor layer on said semiconductor substrate which has a lower impurity concentration than that of said semiconductor substrate; forming a highly doped second semiconductor layer of a second conductivity type in said first semiconductor layer; forming a lightly doped third semiconductor layer of said second conductivity type on said second semiconductor layer; forming a first impurity doped region of said first conductivity type in said third semiconductor layer which is diffused from a surface of said third semiconductor layer by a heating process; and diffusing impurities of first conductivity type of said semiconductor substrate into said first semiconductor layer when said impurity doped region is diffused by said heating process, so as to maintain the impurity concentration of said second semiconductor layer at a constant level and substantially maintain the same thickness.
Claim 3
Dependent Claim
29 words
The method for manufacturing a vertical conducting power semiconductor device according to claim 1, wherein said first, second and third semiconductor layers are formed by an epitaxial growth technique.
Claim 4
Dependent Claim
24 words
The method of manufacturing a vertical conducting power semiconductor device according to claim 1, wherein said first semiconductor layer has said first conductivity type.
Claim 5
Dependent Claim
24 words
The method of manufacturing a vertical conducting power semiconductor device according to claim 1, wherein said first semiconductor layer has said second conductivity type.
Claim 6
Dependent Claim
38 words
The method of manufacturing a vertical conducting power semiconductor device according to claim 1, wherein said first semiconductor layer has a high impurity concentration in the range of 10 18 -10 20 cm -3 by said diffusing step.
Claim 7
Dependent Claim
36 words
The method of manufacturing a vertical conducting power semiconductor device according to claim 1, further comprising the step of forming a second impurity doped region of the second conductivity type within the first impurity doped region.
Claim 8
Dependent Claim
27 words
The method of manufacturing a vertical conducting power semiconductor device according to claim 6, wherein said vertical conducting power semiconductor device is an insulated gate bipolar transistor.
Claim 9
Dependent Claim
38 words
The method of manufacturing a vertical conducting power semiconductor device according to claim 1, further comprising the step of forming a highly doped second conductivity type region in a surface portion of said lightly doped third semiconductor layer.
Claim 10
Dependent Claim
26 words
The method of manufacturing a vertical conducting power semiconductor device according to claim 8, wherein said vertical conducting power semiconductor device is a static induction thyristor.
References Cited (Backward Citations)
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