US4696701A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Epitaxial front seal for a wafer
Assignee: Motorola Solutions Inc
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Filing: 1986-11-12
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Granted: 1987-09-29
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Expires: 2006-11-12
Abstract
Abstract A thin high resistivity epitaxial layer is provided over the entire surface of a semiconductor wafer in order to minimize autodoping while growing a desired epitaxial layer over the entire semiconductor wafer. The thin low resistivity epitaxial layer acts as a seal and is of the same conductivity type as the semiconductor wafer or substrate. The thin epitaxial layer effectively becomes a part of the substrate or semiconductor wafer. The seal layer or thin epitaxial layer is needed when growing an epitaxial layer over a very low resistivity silicon semiconductor wafer.
Inventors
- 👤 Daniel J. Sullivan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 20:11
CPC Classifications
H; H10; H10P; H10P32/00; H10P32/10; H10P32/15; H10W; H10W15/00; H10W15/01; Y; Y10; Y10S; Y10S438/00; Y10S438/914; Y10S438/916
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
113 words
A semiconductor wafer having a seal layer to reduce autodoping during subsequent growth of additional epitaxial layers, comprising: a semiconductor wafer of a first conductivity; a first epitaxial layer covering the semiconductor wafer to serve as the seal layer and being of the first conductivity and having a thickness in the range of 10 to 15 micrometers; and a second epitaxial layer covering the first epitaxial layer, wherein the seal layer has a resistivity of the order of 0.1 ohm cm for an N-type conductivity and a resistivity in the range of 0.5 to 4.5 ohm cm for a P-type conductivity wherein the semiconductor wafer has a maximum resistivity of 0.0055 ohm cm.
Claim 2
Dependent Claim
113 words
A semiconductor wafer having a seal layer to reduce autodoping during subsequent growth of additional epitaxial layers, comprising: a semiconductor wafer of a first conductivity; a first epitaxial layer covering the semiconductor wafer to serve as the seal layer and being of the first conductivity and having a thickness in the range of 10 to 15 micrometers; and a second epitaxial layer covering the first epitaxial layer, wherein the seal layer has a resistivity of the order of 0.1 ohm cm for an N-type conductivity and a resistivity in the range of 0.5 to 4.5 ohm cm for a P-type conductivity wherein the semiconductor wafer has a maximum resistivity of 0.0055 ohm cm.
Claim 3
Dependent Claim
37 words
The semiconductor wafer of claim 1 wherein the resistivity of the semiconductor wafer is adjusted by using an arsenic dopant and the resistivity of the first and second epitaxial layers are adjusted by using a phosphorous dopant.
Claim 4
Dependent Claim
135 words
A silicon wafer having a seal layer to reduce autodoping during growth of an epitaxial layer, comprising: the silicon wafer having a low resistivity of the order of 0.005 ohm cm by being doped with arsenic; a first epitaxial layer covering the wafer and serving as the seal layer wherein the seal layer has a resistivity of approximately one ohm cm and a thickness of approximately ten micrometers; a second epitaxial layer covering the first epitaxial layer and having a resistivity in the range of 3.5 to 5.5 ohm cm and a thickness in the range of 22 to 28 micrometers; and a third epitaxial layer covering the second epitaxial layer and having a resistivity in the range of 45 to 80 ohm cm and a thickness in the range of 54 to 66 micrometers.
Claim 5
Dependent Claim
135 words
A silicon wafer having a seal layer to reduce autodoping during growth of an epitaxial layer, comprising: the silicon wafer having a low resistivity of the order of 0.005 ohm cm by being doped with arsenic; a first epitaxial layer covering the wafer and serving as the seal layer wherein the seal layer has a resistivity of approximately one ohm cm and a thickness of approximately ten micrometers; a second epitaxial layer covering the first epitaxial layer and having a resistivity in the range of 3.5 to 5.5 ohm cm and a thickness in the range of 22 to 28 micrometers; and a third epitaxial layer covering the second epitaxial layer and having a resistivity in the range of 45 to 80 ohm cm and a thickness in the range of 54 to 66 micrometers.
Claim 6
Dependent Claim
35 words
The silicon wafer of claim 3 wherein the first, second, and third epitaxial layers are doped with a phosphorous dopant so that the silicon wafer and all three layers are of the same conductivity type.
Claim 7
Dependent Claim
23 words
The silicon wafer of claim 3 wherein the thickness of the first epitaxial layer is in the range of ten to fifteen micrometers.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1990-09-28 | 1991-03-30 | 1991-09-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-09-28 | 1995-03-30 | 1995-09-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-09-28 | 1999-03-30 | 1999-09-29 | $7700.00 | Window Closed / Lapsed |