Circuit for comparing a plurality of binary inputs

Claim 2

A comparator for receiving M numbers, where M is greater than or equal to three and for generating a signal indicating which of said M numbers are minimum, said comparator comprising: a plurality of two-input comparators each receiving two of said M numbers A 1 , A 2 , . . . , A M , and generating and outputting a signal representing a relation between different numbers A i and A j , where i≠j; and a judging circuit receiving outputs from all of said two-input comparators, and generating and outputting a signal representing which of said M numbers A 1 , A 2 , . . . , A M is minimum.

Claim 3

A comparator for receiving numbers A, B, and C and for generating a signal indicating which of A, B, and C are minimum, said comparator comprising: a first two-input comparator generating and outputting signals P 0 and Q 0 representing a relation between numbers A and B such that (P o , Q 0 )=(1, 0) if A>B, (P 0 , Q 0 )=(0, 1) if A<B, and (P 0 , Q 0 )=(1, 1) if A=B; a second two-input comparator generating and outputting signals P 1 and Q 1 representing a relation between numbers B and C such that (P 1 , Q 1 )=(1, 0) if B>C, (P 1 , Q 1 )=(0, 1) if B<C, and (P 1 , Q 1 )=(1, 1) if B=C; a third two-input comparator generating and outputting signals P 2 and Q 2 representing a relation between numbers C and A such that (P 2 , Q 2 )=(1, 0) if C>A, (P 2 , Q 2 )=(0, 1) if C<A, and (P 2 , Q 2 )=(1, 1) if C=A; and a judging circuit receiving signals P 0 and Q 0 ; P 1 and Q 1 and P 2 and Q 2 , and generating and outputting signals NA, NB, and NC representing which of numbers A, B and C are minimum such that if C is minimum (C<A, B), then (NA, NB, NC)=(0, 0, 1), if B is minimum (B<A, C), then (NA, NB, NC)=(0, 1, 0), if B and C are minimum (B=C<A), then (NA, NB, NC)=(0, 1, 1), if A is minimum (A<B, C), then (NA, NB, NC)=(1, 0, 0), if A and C are minimum (A=C<B), then (NA, NB, NC)=(1, 0, 1), if A and B are minimum (A=B<C), then (NA, NB, NC)=(1, 1, 0), and if A, B and C are equal (A=B=C), then (NA, NB, NC)=(1, 1, 1) in accordance with logic equations: NA=P 2 ·Q 0 NB=P 0 ·Q 1 NC=P 1 ·Q 2 .

Claim 4

A comparator for receiving numbers A, B, and C and for generating a signal indicating which of A, B, and C are minimum, said comparator comprising: a first two-input comparator generating and outputting signals P 0 and Q 0 representing a relation between numbers A and B such that (P o , Q 0 )=(1, 0) if A>B, (P 0 , Q 0 )=(0, 1) if A<B, and (P 0 , Q 0 )=(1, 1) if A=B; a second two-input comparator generating and outputting signals P 1 and Q 1 representing a relation between numbers B and C such that (P 1 , Q 1 )=(1, 0) if B>C, (P 1 , Q 1 )=(0, 1) if B<C, and (P 1 , Q 1 )=(1, 1) if B=C; a third two-input comparator generating and outputting signals P 2 and Q 2 representing a relation between numbers C and A such that (P 2 , Q 2 )=(1, 0) if C>A, (P 2 , Q 2 )=(0, 1) if C<A, and (P 2 , Q 2 )=(1, 1) if C=A; and a judging circuit receiving signals P 0 and Q 0 ; P 1 and Q 1 and P 2 and Q 2 , and generating and outputting signals NA, NB, and NC representing which of numbers A, B and C are minimum such that if C is minimum (C<A, B), then (NA, NB, NC)=(0, 0, 1), if B is minimum (B<A, C), then (NA, NB, NC)=(0, 1, 0), if B and C are minimum (B=C<A), then (NA, NB, NC)=(0, 1, 1), if A is minimum (A<B, C), then (NA, NB, NC)=(1, 0, 0), if A and C are minimum (A=C<B), then (NA, NB, NC)=(1, 0, 1), if A and B are minimum (A=B<C), then (NA, NB, NC)=(1, 1, 0), and if A, B and C are equal (A=B=C), then (NA, NB, NC)=(1, 1, 1) in accordance with logic equations: NA=P 2 ·Q 0 NB=P 0 ·Q 1 NC=P 1 ·Q 2 .

Claim 5

A comparator for receiving M numbers, where M is greater than or equal to three and for generating a signal indicating which of said M numbers are minimum, said comparator comprising: M input registers holding M numbers A 1 , A 2 , . . . , A M ; selectors sequentially selecting outputs A i and A j , where i≠j, from two different input registers in accordance with a selection signal; a two-input comparator receiving numbers A i and A j selected by said selectors, and generating and outputting a comparison result signal representing a relation between numbers A i and A j ; result registers each receiving a comparison result signal from said two-input comparator together with a set signal and holding said comparison result signal until a next set signal is supplied to said result registers; a control circuit generating and outputting said selection signal and said set signal; and a judging circuit receiving outputs from said result registers, and generating and outputting a signal indicating which of said M numbers A 1 , A 2 , . . . , A M is minimum.

Claim 6

A comparator for receiving M numbers, where M is greater than or equal to three and for generating a signal indicating which of said M numbers are minimum, said comparator comprising: M input registers holding M numbers A 1 , A 2 , . . . , A M ; selectors sequentially selecting outputs A i and A j , where i≠j, from two different input registers in accordance with a selection signal; a two-input comparator receiving numbers A i and A j selected by said selectors, and generating and outputting a comparison result signal representing a relation between numbers A i and A j ; result registers each receiving a comparison result signal from said two-input comparator together with a set signal and holding said comparison result signal until a next set signal is supplied to said result registers; a control circuit generating and outputting said selection signal and said set signal; and a judging circuit receiving outputs from said result registers, and generating and outputting a signal indicating which of said M numbers A 1 , A 2 , . . . , A M is minimum.

Claim 7

A comparator for receiving M numbers, where M is greater than or equal to three, and for generating a signal indicating which of said M numbers are maximum, said comparator comprising: a plurality of two-input comparators each receiving two of said M numbers A 1 , A 2 , . . . , A M , and generating and outputting a signal representing a relation between different numbers A i and A j , where i≠j; and a judging circuit receiving outputs from all of said two-input comparators, and generating and outputting a signal representing which of said M numbers A 1 , A 2 , . . . , A M is maximum.

Claim 8

A comparator for receiving M numbers, where M is greater than or equal to three, and for generating a signal indicating which of said M numbers are maximum, said comparator comprising: a plurality of two-input comparators each receiving two of said M numbers A 1 , A 2 , . . . , A M , and generating and outputting a signal representing a relation between different numbers A i and A j , where i≠j; and a judging circuit receiving outputs from all of said two-input comparators, and generating and outputting a signal representing which of said M numbers A 1 , A 2 , . . . , A M is maximum.

Claim 9

A comparator for receiving numbers A, B, and C and for generating a signal indicating which of A, B, and C are maximum, said comparator comprising: a first two-input comparator generating and outputting signals P 0 and Q 0 representing a relation between numbers A and B such that (P 0 , Q 0 )=(1, 0) if A>B, (P 0 , Q 0 )=(0, 1) if A<B, and (P 0 , Q 0 )=(1, 1) if A=B; a second two-input comparator generating and outputting signals P 1 and Q 1 representing a relation between numbers B and C such that (P 1 , Q 1 )=(1, 0) if B>C, (P 1 , Q 1 )=(0, 1) if B<C, and (P 1 , Q 1 )=(1, 1) if B=C; a third two-input comparator generating and outputting signals P 2 and Q 2 representing a relation between numbers C and A such that (P 2 , Q 2 )=(1, 0) if C>A, (P 2 , Q 2 )=(0, 1) if C<A, and (P 2 , Q 2 )=(1, 1) if C=A; and a judging circuit receiving signals P 0 and Q 0 ; P 1 and Q 1 and P 2 and Q 2 and generating and outputting signals XA, XB, and XC representing which of numbers A, B and C are maximum such that if C is maximum (A, B<C), then (XA, XB, XC)=(0, 0, 1), if B is maximum (A, C<B), then (XA, XB, XC)=(0, 1, 0), if B and C are maximum (A<B=C), then (XA, XB, XC)=(0, 1, 1), if A is maximum (B, C<A), then (XA, XB, XC)=(1, 0, 0), if A and C are maximum (B<A=C), then (XA, XB, XC)=(1, 0, 1), if A and B are maximum (C<A=B), then (XA, XB, XC)=(1, 1, 0), and if A, B and C are equal (A=B=C), then (XA, XB, XC)=(1, 1, 1) in accordance with logic equations: XA=P 0 ·Q 2 XB=P 1 ·Q 0 XC=P 2 ·Q 1 .

Claim 10

A comparator for receiving numbers A, B, and C and for generating a signal indicating which of A, B, and C are maximum, said comparator comprising: a first two-input comparator generating and outputting signals P 0 and Q 0 representing a relation between numbers A and B such that (P 0 , Q 0 )=(1, 0) if A>B, (P 0 , Q 0 )=(0, 1) if A<B, and (P 0 , Q 0 )=(1, 1) if A=B; a second two-input comparator generating and outputting signals P 1 and Q 1 representing a relation between numbers B and C such that (P 1 , Q 1 )=(1, 0) if B>C, (P 1 , Q 1 )=(0, 1) if B<C, and (P 1 , Q 1 )=(1, 1) if B=C; a third two-input comparator generating and outputting signals P 2 and Q 2 representing a relation between numbers C and A such that (P 2 , Q 2 )=(1, 0) if C>A, (P 2 , Q 2 )=(0, 1) if C<A, and (P 2 , Q 2 )=(1, 1) if C=A; and a judging circuit receiving signals P 0 and Q 0 ; P 1 and Q 1 and P 2 and Q 2 and generating and outputting signals XA, XB, and XC representing which of numbers A, B and C are maximum such that if C is maximum (A, B<C), then (XA, XB, XC)=(0, 0, 1), if B is maximum (A, C<B), then (XA, XB, XC)=(0, 1, 0), if B and C are maximum (A<B=C), then (XA, XB, XC)=(0, 1, 1), if A is maximum (B, C<A), then (XA, XB, XC)=(1, 0, 0), if A and C are maximum (B<A=C), then (XA, XB, XC)=(1, 0, 1), if A and B are maximum (C<A=B), then (XA, XB, XC)=(1, 1, 0), and if A, B and C are equal (A=B=C), then (XA, XB, XC)=(1, 1, 1) in accordance with logic equations: XA=P 0 ·Q 2 XB=P 1 ·Q 0 XC=P 2 ·Q 1 .

Claim 11

A comparator for receiving M numbers, where M is greater than or equal to three, and for generating a signal indicating which of said M numbers are maximum, said comparator comprising: M input registers holding M numbers A 1 , A 2 , . . . , A M ; selectors sequentially selecting outputs A 1 and A j , where i≠j, from two different input registers in accordance with a selection signal; a two-input comparator receiving numbers A i and A j selected by said selectors, and generating and outputting a comparison result signal representing a relation between numbers A i and A j ; result registers each receiving a comparison result signal from said two-input comparator together with a set signal and holding said comparison result signal until a next set signal is supplied to said result registers; a control circuit generating and outputting said selection signal and said set signal; and a judging circuit receiving outputs from said result registers, and generating and outputting a signal indicating which of said M numbers A 1 , A 2 , . . . , A M is maximum.

Claim 12

A comparator for receiving M numbers, where M is greater than or equal to three, and for generating a signal indicating which of said M numbers are maximum, said comparator comprising: M input registers holding M numbers A 1 , A 2 , . . . , A M ; selectors sequentially selecting outputs A 1 and A j , where i≠j, from two different input registers in accordance with a selection signal; a two-input comparator receiving numbers A i and A j selected by said selectors, and generating and outputting a comparison result signal representing a relation between numbers A i and A j ; result registers each receiving a comparison result signal from said two-input comparator together with a set signal and holding said comparison result signal until a next set signal is supplied to said result registers; a control circuit generating and outputting said selection signal and said set signal; and a judging circuit receiving outputs from said result registers, and generating and outputting a signal indicating which of said M numbers A 1 , A 2 , . . . , A M is maximum.