Circuit for selecting one of a plurality of exponential values to a predetermined base to provide a maximum value

Claim 2

A circuit for receiving a plurality of input operands representing exponential values relative to a predetermined base value which is less than one and selecting the operand which when used as an exponent of the base value represents a maximum value, comprising: first transcoder means for sequentially receiving each of the input operands and providing a first intermediate operand in response to each received operand, each of the first intermediate operands indicating the bit position of a most significant bit of the respective input operand; logic means coupled to the first transcoder means for selectively receiving the first intermediate operands and comparing a most recently received first intermediate operand with a previous maximum value first intermediate operand to provide a second intermediate operand which represents the maximum valued operand of all of the previously received first intermediate operands including the most recently received first intermediate operand; and second transcoder means coupled to the logic means for selectively receiving the second intermediate operands and transcoding each received second intermediate operand to provide an output indicating the one of the plurality of input operands which raises the base value to the maximum value.

Claim 3

The circuit of claim 1 wherein the input operands are signed operands and the circuit further comprises: sign control means for receiving a sign bit of each signed input operand and providing an output sign bit of the maximum value, said sign control means further providing control signals to the first and second transcoder means and to the logic means to control said circuit.

Claim 4

The circuit of claim 1 wherein the logic means further comprises a logic coupled to a latch circuit, said logic gate receiving the first intermediate operand and said latch circuit providing the second intermediate operand.

Claim 5

A circuit for receiving a plurality of input operands representing exponential values relative to a predetermined base less than one and providing the operand which when used as an exponent of the base value represents a maximum value, comprising: first logic means for sequentially receiving each of the input operands and providing a first intermediate operand in response to each operand, each of said first intermediate operands indicating the bit position of a most significant bit of the respective input operand; second logic means having a first input for receiving the first intermediate operand, a second input and an output, said second logic means performing a predetermined logic function with said first and second inputs; storage means having an input coupled to the output of the second logic means, and an output coupled to the second input of the second logic means for storing and providing a second intermediate operand which represents the one of all of the previously received first intermediate operands including the most recently received first intermediate operand which raises the base value to the maximum value; and third logic means coupled to the storage means for selectively receiving the second intermediate operands and transcoding the second intermediate operands to provide an output indicating the one of the plurality of input operands which raises the base value to the maximum value.

Claim 6

A circuit for receiving a plurality of input operands representing exponential values relative to a predetermined base less than one and providing the operand which when used as an exponent of the base value represents a maximum value, comprising: first logic means for sequentially receiving each of the input operands and providing a first intermediate operand in response to each operand, each of said first intermediate operands indicating the bit position of a most significant bit of the respective input operand; second logic means having a first input for receiving the first intermediate operand, a second input and an output, said second logic means performing a predetermined logic function with said first and second inputs; storage means having an input coupled to the output of the second logic means, and an output coupled to the second input of the second logic means for storing and providing a second intermediate operand which represents the one of all of the previously received first intermediate operands including the most recently received first intermediate operand which raises the base value to the maximum value; and third logic means coupled to the storage means for selectively receiving the second intermediate operands and transcoding the second intermediate operands to provide an output indicating the one of the plurality of input operands which raises the base value to the maximum value.

Claim 7

The circuit of claim 4 wherein the second logic means is an AND gate.

Claim 8

The circuit of claim 4 wherein the storage means is a D-type flip flop.

Claim 9

The circuit of claim 4 wherein the input operands are signed operands and the circuit further comprises: sign control means for receiving a sign bit of each signed input operand and providing an output sign bit of the maximum value, said sign control means further providing control signals to the first and third logic means and storage means to control the operation of said circuit.