Method and apparatus for the recording and replay of interlaced signals

Claim 2

Apparatus for recording in a memory an interlaced input signal having an input even field, an input odd field, an even field vertical synchronization signal and even field horizontal synchronization signals associated with said even field, and an odd field vertical synchronization signal and odd field horizontal synchronization signals associated with said odd field, comprising input means for receiving said interlaced signal; first means connected to said input means and responsive at least in part to said vertical synchronization signals for generating field signals selecting one of said fields as output top field and the other of said fields as output bottom field; and timing means connected to said first means and responsive at least in part to said horizontal synchronization signals for generating a first selector signal indicative of the presence of an output top field and a second selector signal indicative of the presence of an output bottom field, respectively, in response to said field signals.

Claim 3

Apparatus as set forth in claim 1, wherein said field signals comprise a first field signal selecting the then present field as top field and a second field signal selecting the next following field as bottom field; and wherein said timing means generates said first selector signal in response to said first field signal and said second selector signal in response to said second field signal.

Claim 4

Apparatus as set forth in claim 2, further comprising means for applying said second selector signal to said first means, so that said first means furnishes said first field signal only in response to a vertical synchronization signal received in the presence of said second selector signal.

Claim 5

Apparatus as set forth in claim 3, further comprising counting means having a clock input, a reset input and a terminal count output furnishing a terminal count signal upon receipt of a predetermined number of horizontal synchronization signals following reset of said counting means; first connecting means for connecting said first means to said reset input for resetting said counting means in response to said first field signal; and means for applying said horizontal synchronization signals to said clock input.

Claim 6

Apparatus as set forth in claim 4, wherein said first means comprises gating means having a gating input for generating said second field signal in response to a gating signal at said gating input; and means for connecting said terminal count output of said counting means to said gating input so that said second field signal occurs upon receipt of said terminal count signal.

Claim 7

Apparatus as set forth in claim 5, wherein said terminal count signal is furnished at a count of 5.

Claim 8

Apparatus as set forth in claim 1, wherein said timing means comprises means for furnishing a regenerated vertical synchronization signal in response to each of said field signals and for terminating each of said regenerated vertical synchronization signals following receipt of a predetermined number of horizontal synchronization signals.

Claim 9

Apparatus as set forth in claim 7, wherein said timing means further comprises flip-flop means having a Q output having a first state furnishing said first selector signal and a second state furnishing said second selector signal, and a clock input receiving said regenerated vertical synchronization signal, whereby said state of said Q output of said flip-flop means changes in response to said regenerated vertical synchronization signal.

Claim 10

Apparatus as set forth in claim 4, wherein said interlaced input signal is a television signal.

Claim 11

Apparatus as set forth in claim 9, wherein each of said fields of said television signal comprises a first plurality of lines, said first plurality of lines comprising a second plurality of lines having video information to be displayed; further comprising top line counter means connected to said timing means, for counting horizontal synchronization signals following receipt of each of said selector signals and generating a top line signal when the count on said top line counter means is indicative of the presence of the first of said second plurality of lines.

Claim 12

Apparatus as set forth in claim 9, wherein said television signal has an NTSC format and wherein said counting means counts to a count of 5.

Claim 13

Apparatus as set forth in claim 9, wherein said television signal has a PAL format and said counting means counts to a count of 5.

Claim 14

Apparatus as set forth in claim 4, wherein said even field and said odd field each comprises a plurality of lines; further comprising horizontal window signal furnishing means for generating a horizontal window having a first value for a first predetermined time period including occurrence of a horizontal synchronization signal in each of said lines, and a second value for the remainder of each of said lines; further comprising means for blocking said vertical synchronization signals from said first means while said horizontal window signal has said first value during said output bottom field, and for transmitting the remaining ones of said vertical synchronization signals thereby generating VGATE signals.

Claim 15

Apparatus as set forth in claim 13, wherein said blocking means comprises a NAND gate.

Claim 16

Apparatus as set forth in claim 13, further comprising means connected to said blocking means for applying said VGATE signals to said first means for gating said first selector signal and said terminal count signal.

Claim 17

Apparatus as set forth in claim 15, wherein said first selector signal and said second selector signal together constitute a binary field signal having a first value constituting said first selector signal and a second value constituting said second selector signal.

Claim 18

Method for generating a first selector signal selecting an even field or an odd field of an input interlaced signal as top field and a second selector signal selecting the other of said even field and said odd field as bottom field, said even field and said odd field having, respectively, even field and odd field vertical synchronization signals, each of said vertical synchronization signals having a sequence of horizontal synchronization signals associated therewith, comprising the steps of separating said even and odd input vertical synchronization signals and said associated horizontal synchronization signals from said even and odd fields; generating a first regenerated vertical synchronization signal in response to said even field input vertical synchronization signal or said odd field input vertical synchronization signals and a predetermined one of the sequence of horizontal synchronization signals associated therewith; generating a second regenerated vertical synchronization signal in response to the other of said input vertical synchronization signals and a selected one of said sequence of horizontal synchronization signals associated therewith; and generating said first selector signal and said second selector signal in response to said first and second regenerated vertical synchronization signal, respectively.

Claim 19

Method for generating a first selector signal selecting an even field or an odd field of an input interlaced signal as top field and a second selector signal selecting the other of said even field and said odd field as bottom field, said even field and said odd field having, respectively, even field and odd field vertical synchronization signals, each of said vertical synchronization signals having a sequence of horizontal synchronization signals associated therewith, comprising the steps of separating said even and odd input vertical synchronization signals and said associated horizontal synchronization signals from said even and odd fields; generating a first regenerated vertical synchronization signal in response to said even field input vertical synchronization signal or said odd field input vertical synchronization signals and a predetermined one of the sequence of horizontal synchronization signals associated therewith; generating a second regenerated vertical synchronization signal in response to the other of said input vertical synchronization signals and a selected one of said sequence of horizontal synchronization signals associated therewith; and generating said first selector signal and said second selector signal in response to said first and second regenerated vertical synchronization signal, respectively.

Claim 20

The method as set forth in claim 17, wherein said second regenerated vertical synchronization signal is substantially equal to said first regenerated vertical synchronization signal and alternates therewith in time.

Claim 21

The method as set forth in claim 18, wherein said first regenerated vertical synchronization signal is generated in response to said even field vertical synchronization signal and said second regenerated vertical synchronization signal is generated in response to said odd field vertical synchronization signal, whereby said even field constitutes top field and said odd field constitutes bottom field.

Claim 22

A method as set forth in claim 19, wherein said predetermined one of said sequence of associated horizontal synchronization signals is the horizontal synchronization signal immediately following said even field vertical synchronization signal.

Claim 23

A method as set forth in claim 20, wherein said preselected one of said input horizontal synchronization signals is a second horizontal synchronization signal other than the input horizontal synchronization signal immediately following said odd field input vertical synchronization signal.

Claim 24

A method as set forth in claim 21, further comprising the step of counting horizontal synchronization signals repetitively from a first count to a terminal count in response to a reset signal; generating said reset signal in response to said even field horizontal synchronization signal immediately following said even field vertical synchronization signal; and wherein said preselected one of said sequence of odd field horizontal synchronization signals is the odd field horizontal synchronization signal immediately following said terminal count.

Claim 25

A method as set forth in claim 18, further comprising window signal generating means for generating a window signal blocking vertical synchronization signals occurring within a predetermined time frame around a horizontal synchronization signal; and further comprising the step of generating said first regenerated vertical synchronization signal in response to said odd field vertical synchronization signal and said second regenerated vertical synchronization signal in response to a subsequent even field vertical synchronization signal, whereby said odd field constitutes top field and said even field constitutes bottom field when said even field vertical synchronization signal occurs within said time frame.

Claim 26

A method as set forth in claim 18, wherein said input signal is a received signal having an information content; further comprising the step of storing said information content in memory at least in part under control of said first selector signals.

Claim 27

A method as set forth in claim 18, wherein said input interlaced signal is stored in memory; further comprising the step of reading said input interlaced signal from memory at least in part under control of said first selector signal.

Claim 28

Apparatus for reading from a memory an interlaced input signal having an input even field, an input odd field, an even field vertical synchronization signal and even field horizontal synchronization signals associated with said even field, and an odd field vertical synchronization signal and odd field horizontal synchronization signals associated with said odd field, comprising readout means for reading said interlaced signal from said memory; first means responsive at least in part to said vertical synchronization signals for generating field signals selecting one of said fields as output top field and the other of said fields as output bottom field; and timing means connected to said first means and responsive at least in part to said horizontal synchronization signals for generating a first selector signal indicative of the presence of an output top field and a second selector signal indicative of the presence of an output bottom field, respectively, in response to said field signals.

Claim 29

Apparatus for reading from a memory an interlaced input signal having an input even field, an input odd field, an even field vertical synchronization signal and even field horizontal synchronization signals associated with said even field, and an odd field vertical synchronization signal and odd field horizontal synchronization signals associated with said odd field, comprising readout means for reading said interlaced signal from said memory; first means responsive at least in part to said vertical synchronization signals for generating field signals selecting one of said fields as output top field and the other of said fields as output bottom field; and timing means connected to said first means and responsive at least in part to said horizontal synchronization signals for generating a first selector signal indicative of the presence of an output top field and a second selector signal indicative of the presence of an output bottom field, respectively, in response to said field signals.

Claim 30

Apparatus receiving at least a first and second interlaced signal each having a first field interlaced with a second field and having, respectively, first and second synchronization signals, for furnishing a first and second display, respectively, in response thereto, comprising: first means for arbitrarily selecting one of said interlaced fields of said first signal as first top field, and the other of said fields as first bottom field; memory means; second means for recording said first top field and said first bottom field in said memory means under control of said first synchronization signals, thereby creating a stored top field and a stored bottom field, respectively; display means; and third means for reading said stored top field and said stored bottom field from said memory means under control of said second synchronization signals and in conjunction with said second signal so that a first display and a second display, corresponding, respectively to said first signal and said second signal, are created on said display means.

Claim 31

Apparatus receiving at least a first and second interlaced signal each having a first field interlaced with a second field and having, respectively, first and second synchronization signals, for furnishing a first and second display, respectively, in response thereto, comprising: first means for arbitrarily selecting one of said interlaced fields of said first signal as first top field, and the other of said fields as first bottom field; memory means; second means for recording said first top field and said first bottom field in said memory means under control of said first synchronization signals, thereby creating a stored top field and a stored bottom field, respectively; display means; and third means for reading said stored top field and said stored bottom field from said memory means under control of said second synchronization signals and in conjunction with said second signal so that a first display and a second display, corresponding, respectively to said first signal and said second signal, are created on said display means.

Claim 32

Apparatus as set forth in claim 27, wherein said first synchronization signals comprise first vertical synchronization signals and first horizontal synchronization signals; wherein said first means comprises means for generating a top field signal indicative of top field in response to a vertical synchronization signal followed by a horizontal synchronization signal of said first or said second interlaced signal, and counting means reset in response to said top field signal for counting horizontal synchronization signals, and for generating a bottom field signal indicative of bottom field upon receipt of the subsequent one of said vertical synchronization signals and a predetermined count on said counting means.