Interlace inversion detector for a picture-in-picture video signal generator

Claim 2

In a picture-in-picture video signal generator comprising: a source of an auxiliary video signal; an auxiliary synchronization component separator, coupled to said auxiliary video signal source, for producing an auxiliary odd/even signal indicating whether a current field of said auxiliary video is an odd field or an even field; a memory, coupled to said auxiliary video signal source, for storing data representing said auxiliary video signal and subsequently retrieving said data; a source of main video signal; a main synchronization component separator, coupled to said main video signal source, for producing a main odd/even source indicating whether a current field of said main video signal is an odd field or an even field; means, coupled to said main video signal source and said memory, for inserting a signal representing said retrieved data from said memory into a portion of said main video signal to form said picture in picture video signal; interlace inversion detector means, coupled to said main and auxiliary synchronization component separators, for generating a detector output signal having a first state when either: odd field auxiliary video signal information is retrieved from said memory during an even field of said main video signal, or even field auxiliary video signal information is retrieved from said memory during an odd field of said main video signal, and having a second state otherwise; and means for correcting said interlace invesion responsive to said detector output signal.

Claim 3

In a picture-in-picture video signal generator comprising: a source of an auxiliary video signal; an auxiliary synchronization component separator, coupled to said auxiliary video signal source, for producing an auxiliary odd/even signal indicating whether a current field of said auxiliary video signal is an odd field, or an even field a memory, coupled to said auxiliary video signal source, for storing data representing said auxiliary video signal and subsequently retrieving said data; a source of a main video signal; a main synchronization component separator, coupled to said main video signal source, for producing a main odd/even signal indicating whether a current field of said main video signal is an odd field or an even field; means, coupled to said main video signal source and said memroy, for inserting a signal representing said retrieved data from said memroy into a portion of said main video signal to form said picture-in-picture video signal; interlace inversion detector means, coupled to said main and auxiliary synchronization component separators, and including a D flip-flop having a clock input terminal responsive to said auxiliary odd/even signal, a D input temrinal responsive to said main odd/even signal, and a Q output terminal for producing a detector output signal, having a first state when either: odd field auxiliary video signal information is retrieved from said memory during an even field of said main video signal, or even field auxiliary video signal information is retrieved from said memory during an odd field of said main video signal, and having a second state otherwise; and means for correcting said interlace inversion responsive to said detector output signal.

Claim 4

In a picture-in-picture video signal generator comprising: a source of an auxiliary video signal; an auxiliary synchronization component separator, coupled to said auxiliary video signal source, for producing an auxiliary odd/even signal indicating whether a current field of said auxiliary video signal is an odd field, or an even field a memory, coupled to said auxiliary video signal source, for storing data representing said auxiliary video signal and subsequently retrieving said data; a source of a main video signal; a main synchronization component separator, coupled to said main video signal source, for producing a main odd/even signal indicating whether a current field of said main video signal is an odd field or an even field; means, coupled to said main video signal source and said memroy, for inserting a signal representing said retrieved data from said memroy into a portion of said main video signal to form said picture-in-picture video signal; interlace inversion detector means, coupled to said main and auxiliary synchronization component separators, and including a D flip-flop having a clock input terminal responsive to said auxiliary odd/even signal, a D input temrinal responsive to said main odd/even signal, and a Q output terminal for producing a detector output signal, having a first state when either: odd field auxiliary video signal information is retrieved from said memory during an even field of said main video signal, or even field auxiliary video signal information is retrieved from said memory during an odd field of said main video signal, and having a second state otherwise; and means for correcting said interlace inversion responsive to said detector output signal.

Claim 5

The signal generator for claim 2, wherein said interlace inversion corrector corrects alternate fields of said picture-in-picture video signal, and comprises: an AND gate having a first input terminal responsive to said main odd/even signal, a second input terminal coupled to said Q output terminal of said D flip-flop, and an output terminal for producing said detector output signal.

Claim 6

The signal generator of claim 3, wherein said interlace inversion corrector further includes an inverter responsive to said main odd/even signal, and having an output terminal coupled to said second input terminal of said AND gate.