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US4916671A
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Semiconductor memory device having sense amplifier having improved activation timing thereof and operating method thereof
Assignee: Mitsubishi Electric Corp
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Filing: 1989-02-22
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Granted: 1990-04-10
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Expires: 2009-02-22
Abstract
Abstract A dynamic random access memory comprises memory cells (MA1-Man) and sense amplifies (SA1-SAn) in a memory array region III and memory cells (MB1-MBn) and sense amplifies (SB1-SBn) in a memory array region IV. In reading operation, first, the sense amplifiers in one region comprising a memory cell designated by an address signal are activated and then sense amplifiers in the other region are activated. As a result, since amplifying operation by the sense amplifiers is performed sequentially, a peak value of a current consumed by the amplification can be reduced.
Inventors
- 👤 Tetsuichiro Ichiguchi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 06:38
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/06; G11C7/065
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
184 words
A semiconductor memory device comprising: a memory array (58) comprising a plurality of memory cells for storing a data signal; means (54) for receiving address signals to select a memory cell in said memory array (58), said memory array (58) comprising a first memory array region including a memory cell selected by said address signals and a second memory array region not including the selected memory cell; first amplifying means connected to said first memory array region of said memory array (58) for amplifying the data signal stored in the memory cell in said first memory array region; second amplifying means connected to said second memory array region of said memory array (58) for amplifying the data signal stored in a memory cell in said second memory array region; and sequentially activating means (64) connected to said first and second amplifying means for activating said first and second amplifying means in sequential order in response to the address signals, thereby sequentially amplifying data stored in memory cells in said first and second memory array regions whereby a peak value of current consumption is reduced.
Claim 2
Dependent Claim
184 words
A semiconductor memory device comprising: a memory array (58) comprising a plurality of memory cells for storing a data signal; means (54) for receiving address signals to select a memory cell in said memory array (58), said memory array (58) comprising a first memory array region including a memory cell selected by said address signals and a second memory array region not including the selected memory cell; first amplifying means connected to said first memory array region of said memory array (58) for amplifying the data signal stored in the memory cell in said first memory array region; second amplifying means connected to said second memory array region of said memory array (58) for amplifying the data signal stored in a memory cell in said second memory array region; and sequentially activating means (64) connected to said first and second amplifying means for activating said first and second amplifying means in sequential order in response to the address signals, thereby sequentially amplifying data stored in memory cells in said first and second memory array regions whereby a peak value of current consumption is reduced.
Claim 3
Dependent Claim
45 words
A semiconductor memory device in accordance with claim 1, wherein said address signals comprise a row address signal and a column address signal and said first and second memory array regions are selected in response to the row address signal and the column address signal.
Claim 4
Dependent Claim
249 words
A semiconductor memory device comprising: a memory array (58) including a plurality of memory cells for storing a data signal; means (54) for receiving address signals to select a memory cell in said memory array (58), said memory array (58) comprising a first memory array region including a memory cell selected by said address signals and a second memory array region not including the selected memory cell; first amplifying means connected to said first memory array region of said memory array (58) for amplifying the data signal stored in the memory cell in said first memory array region; second amplifying means connected to said second memory array region of said memory array (58) for amplifying the data signal stored in a memory cell in said second memory array region; and sequentially activating means (64) connected to said first and second amplifying means for activating said first and second amplifying means in sequential order in response to the address signals, wherein said first amplifying means comprises: first sense amplifier means comprising field effect devices of one conductivity type; and second sense amplifier means comprising field effect devices of the other conductivity type, said first and second sense amplifier means constituting first complementary sense amplifier means, and said second amplifying means comprises: third sense amplifier means comprising field effect devices on one conductivity type; and fourth sense amplifier means comprising field effect devices of the other conductivity type, said third and fourth sense amplifier means constituting second complementary sense amplifier means.
Claim 5
Dependent Claim
249 words
A semiconductor memory device comprising: a memory array (58) including a plurality of memory cells for storing a data signal; means (54) for receiving address signals to select a memory cell in said memory array (58), said memory array (58) comprising a first memory array region including a memory cell selected by said address signals and a second memory array region not including the selected memory cell; first amplifying means connected to said first memory array region of said memory array (58) for amplifying the data signal stored in the memory cell in said first memory array region; second amplifying means connected to said second memory array region of said memory array (58) for amplifying the data signal stored in a memory cell in said second memory array region; and sequentially activating means (64) connected to said first and second amplifying means for activating said first and second amplifying means in sequential order in response to the address signals, wherein said first amplifying means comprises: first sense amplifier means comprising field effect devices of one conductivity type; and second sense amplifier means comprising field effect devices of the other conductivity type, said first and second sense amplifier means constituting first complementary sense amplifier means, and said second amplifying means comprises: third sense amplifier means comprising field effect devices on one conductivity type; and fourth sense amplifier means comprising field effect devices of the other conductivity type, said third and fourth sense amplifier means constituting second complementary sense amplifier means.
Claim 6
Dependent Claim
33 words
A semiconductor memory device in accordance with claim 3, wherein said sequentially activating means (64) activates said first and second complementary sense amplifier means in sequential order in response to an address signal.
Claim 7
Dependent Claim
32 words
A semiconductor memory device in accordance with claim 3, wherein said sequentially activating means (64) activates said first and third sense amplifier means in sequential order in response to an address signal.
Claim 8
Dependent Claim
27 words
A semiconductor memory device in accordance with claim 3, wherein said one conductivity type comprises a P type and said other conductivity type comprises an N type.
Claim 9
Dependent Claim
165 words
A semiconductor memory device comprising a dynamic random access memory, including: a memory array (58) comprising a plurality of memory cells for storing a data signal; means (54) for receiving address signals to select a memory cell in said memory array (58), said memory array (58) comprising a first memory array region including a memory cell selected by said address signals and a second memory array region not including the selected memory cell; first amplifying means connected to said first memory array region of said memory array (58) for amplifying the data signal stored in the memory cell in said first memory array region; second amplifying means connected to said second memory array region of said memory array (58) for amplifying the data signal stored in a memory cell in said second memory array region; and sequentially activating means (64) connected to said first and second amplifying means for activating said first and second amplifying means in sequential order in response to the address signals.
Claim 10
Dependent Claim
165 words
A semiconductor memory device comprising a dynamic random access memory, including: a memory array (58) comprising a plurality of memory cells for storing a data signal; means (54) for receiving address signals to select a memory cell in said memory array (58), said memory array (58) comprising a first memory array region including a memory cell selected by said address signals and a second memory array region not including the selected memory cell; first amplifying means connected to said first memory array region of said memory array (58) for amplifying the data signal stored in the memory cell in said first memory array region; second amplifying means connected to said second memory array region of said memory array (58) for amplifying the data signal stored in a memory cell in said second memory array region; and sequentially activating means (64) connected to said first and second amplifying means for activating said first and second amplifying means in sequential order in response to the address signals.
Claim 11
Independent Claim
179 words
A method for operating a semiconductor memory device comprising a memory array (58) including a plurality of memory cells for storing a data signal, said method comprising the steps of: receiving address signals for selecting a memory cell in said memory array (58), said memory array (58) being capable of being selectively divided into a first memory array region comprising the memory cell selected by said address signal and a second memory array region not including the selected memory cell; amplifying the data signal stored in the memory cell in said first memory array region in response to the address signal; and amplifying the data signal stored in a memory cell in said second memory array region in response to the address signals, the data signal from a memory cell in said first memory array region being amplified before the data signal from a memory cell in said second memory array region is amplified whereby a peak value of current consumption is reduced by sequentially amplifying data stored in memory cells in said first and second memory array regions.
Claim 12
Independent Claim
179 words
A method for operating a semiconductor memory device comprising a memory array (58) including a plurality of memory cells for storing a data signal, said method comprising the steps of: receiving address signals for selecting a memory cell in said memory array (58), said memory array (58) being capable of being selectively divided into a first memory array region comprising the memory cell selected by said address signal and a second memory array region not including the selected memory cell; amplifying the data signal stored in the memory cell in said first memory array region in response to the address signal; and amplifying the data signal stored in a memory cell in said second memory array region in response to the address signals, the data signal from a memory cell in said first memory array region being amplified before the data signal from a memory cell in said second memory array region is amplified whereby a peak value of current consumption is reduced by sequentially amplifying data stored in memory cells in said first and second memory array regions.
Claim 13
Dependent Claim
18 words
A method in accordance with claim 8, wherein said semiconductor memory device comprises a dynamic random access memory.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-04-09 | 1993-10-09 | 1994-04-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-04-09 | 1997-10-09 | 1998-04-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-04-09 | 2001-10-09 | 2002-04-10 | $7700.00 | Window Closed / Lapsed |